^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2012 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static int clk_busy_wait(void __iomem *reg, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned long timeout = jiffies + msecs_to_jiffies(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) while (readl_relaxed(reg) & (1 << shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_busy_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk_divider div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) const struct clk_ops *div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clk_divider *div = to_clk_divider(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return container_of(div, struct clk_busy_divider, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static unsigned long clk_busy_divider_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk_busy_divider *busy = to_clk_busy_divider(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static long clk_busy_divider_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk_busy_divider *busy = to_clk_busy_divider(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return busy->div_ops->round_rate(&busy->div.hw, rate, prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int clk_busy_divider_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clk_busy_divider *busy = to_clk_busy_divider(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = clk_busy_wait(busy->reg, busy->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct clk_ops clk_busy_divider_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .recalc_rate = clk_busy_divider_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .round_rate = clk_busy_divider_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .set_rate = clk_busy_divider_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void __iomem *busy_reg, u8 busy_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk_busy_divider *busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) busy = kzalloc(sizeof(*busy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) busy->reg = busy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) busy->shift = busy_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) busy->div.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) busy->div.shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) busy->div.width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) busy->div.lock = &imx_ccm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) busy->div_ops = &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) init.ops = &clk_busy_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) init.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) busy->div.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) hw = &busy->div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) kfree(busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk_busy_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const struct clk_ops *mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk_mux *mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return container_of(mux, struct clk_busy_mux, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static u8 clk_busy_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct clk_busy_mux *busy = to_clk_busy_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return busy->mux_ops->get_parent(&busy->mux.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk_busy_mux *busy = to_clk_busy_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = busy->mux_ops->set_parent(&busy->mux.hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = clk_busy_wait(busy->reg, busy->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct clk_ops clk_busy_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .get_parent = clk_busy_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .set_parent = clk_busy_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 width, void __iomem *busy_reg, u8 busy_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const char * const *parent_names, int num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct clk_busy_mux *busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) busy = kzalloc(sizeof(*busy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) busy->reg = busy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) busy->shift = busy_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) busy->mux.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) busy->mux.shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) busy->mux.mask = BIT(width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) busy->mux.lock = &imx_ccm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) busy->mux_ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) init.ops = &clk_busy_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) init.flags = CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) busy->mux.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) hw = &busy->mux.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) kfree(busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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