^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016-2017 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Paul Burton <paul.burton@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define pr_fmt(fmt) "clk-boston: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/boston-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BOSTON_PLAT_MMCMDIV 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) # define BOSTON_PLAT_MMCMDIV_CLK0DIV (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) # define BOSTON_PLAT_MMCMDIV_INPUT (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) # define BOSTON_PLAT_MMCMDIV_MUL (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # define BOSTON_PLAT_MMCMDIV_CLK1DIV (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BOSTON_CLK_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static u32 ext_field(u32 val, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return (val & mask) >> (ffs(mask) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void __init clk_boston_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long in_freq, cpu_freq, sys_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) uint mmcmdiv, mul, cpu_div, sys_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk_hw_onecell_data *onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) regmap = syscon_node_to_regmap(np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pr_err("failed to find regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) err = regmap_read(regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pr_err("failed to read mmcm_div register: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) in_freq = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT) * 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) sys_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) sys_freq = mult_frac(in_freq, mul, sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) cpu_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) cpu_freq = mult_frac(in_freq, mul, cpu_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) onecell = kzalloc(struct_size(onecell, hws, BOSTON_CLK_COUNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!onecell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) onecell->num = BOSTON_CLK_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pr_err("failed to register input clock: %ld\n", PTR_ERR(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) goto fail_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) onecell->hws[BOSTON_CLK_INPUT] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) goto fail_sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) onecell->hws[BOSTON_CLK_SYS] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) goto fail_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) onecell->hws[BOSTON_CLK_CPU] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, onecell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pr_err("failed to add DT provider: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto fail_clk_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) fail_clk_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_CPU]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) fail_cpu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) fail_sys:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) fail_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) kfree(onecell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Use CLK_OF_DECLARE so that this driver is probed early enough to provide the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * CPU frequency for use with the GIC or cop0 counters/timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CLK_OF_DECLARE(clk_boston, "img,boston-clock", clk_boston_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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