^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * HiSilicon Clock and Reset Driver Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 HiSilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __HISI_CRG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __HISI_CRG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct hisi_clock_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct hisi_reset_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct hisi_crg_funcs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) void (*unregister_clks)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct hisi_crg_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct hisi_reset_controller *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) const struct hisi_crg_funcs *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif /* __HISI_CRG_H */