^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hi3798CV200 Clock and Reset Generator Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <dt-bindings/clock/histb-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "crg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* hi3798CV200 core CRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HI3798CV200_INNER_CLK_OFFSET 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HI3798CV200_FIXED_24M 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HI3798CV200_FIXED_25M 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HI3798CV200_FIXED_50M 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HI3798CV200_FIXED_75M 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HI3798CV200_FIXED_100M 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HI3798CV200_FIXED_150M 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HI3798CV200_FIXED_200M 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HI3798CV200_FIXED_250M 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HI3798CV200_FIXED_300M 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HI3798CV200_FIXED_400M 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HI3798CV200_MMC_MUX 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HI3798CV200_ETH_PUB_CLK 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HI3798CV200_ETH_BUS_CLK 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HI3798CV200_ETH_BUS0_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HI3798CV200_ETH_BUS1_CLK 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HI3798CV200_COMBPHY1_MUX 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HI3798CV200_FIXED_12M 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HI3798CV200_FIXED_48M 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HI3798CV200_FIXED_60M 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HI3798CV200_FIXED_166P5M 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HI3798CV200_SDIO0_MUX 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HI3798CV200_COMBPHY0_MUX 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HI3798CV200_CRG_NR_CLKS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const char *const mmc_mux_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "100m", "50m", "25m", "200m", "150m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const char *const comphy_mux_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "100m", "25m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static u32 comphy_mux_table[] = {2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const char *const sdio_mux_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "100m", "50m", "150m", "166p5m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static u32 sdio_mux_table[] = {0, 1, 2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { HI3798CV200_COMBPHY0_MUX, "combphy0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x9c, 8, 2, 0, sdio_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static u32 mmc_phase_degrees[] = {0, 45, 90, 135, 180, 225, 270, 315};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct hisi_phase_clock hi3798cv200_phase_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { HISTB_UART2_CLK, "clk_uart2", "75m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CLK_SET_RATE_PARENT, 0x68, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { HISTB_I2C3_CLK, "clk_i2c3", "clk_apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { HISTB_I2C4_CLK, "clk_i2c4", "clk_apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { HISTB_SPI0_CLK, "clk_spi0", "clk_apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) CLK_SET_RATE_PARENT, 0x70, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* EMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* PCIE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CLK_SET_RATE_PARENT, 0xcc, 24, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* COMBPHY0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { HISTB_COMBPHY0_CLK, "clk_combphy0", "combphy0_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CLK_SET_RATE_PARENT, 0x188, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* COMBPHY1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLK_SET_RATE_PARENT, 0x188, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* USB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* USB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) CLK_SET_RATE_PARENT, 0xb0, 16, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CLK_SET_RATE_PARENT, 0xb0, 20, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CLK_SET_RATE_PARENT, 0xb0, 19, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct hisi_clock_data *hi3798cv200_clk_register(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* hisi_phase_clock is resource managed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = hisi_clk_register_phase(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) hi3798cv200_phase_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ARRAY_SIZE(hi3798cv200_phase_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ARRAY_SIZE(hi3798cv200_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto unregister_fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ARRAY_SIZE(hi3798cv200_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto unregister_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = of_clk_add_provider(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) of_clk_src_onecell_get, &clk_data->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto unregister_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unregister_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) hisi_clk_unregister_gate(hi3798cv200_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ARRAY_SIZE(hi3798cv200_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unregister_mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) hisi_clk_unregister_mux(hi3798cv200_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ARRAY_SIZE(hi3798cv200_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unregister_fixed_rate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void hi3798cv200_clk_unregister(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) hisi_clk_unregister_gate(hi3798cv200_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ARRAY_SIZE(hi3798cv200_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) hisi_clk_unregister_mux(hi3798cv200_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ARRAY_SIZE(hi3798cv200_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .register_clks = hi3798cv200_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .unregister_clks = hi3798cv200_clk_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* hi3798CV200 sysctrl CRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HI3798CV200_SYSCTRL_NR_CLKS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { HISTB_IR_CLK, "clk_ir", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) CLK_SET_RATE_PARENT, 0x48, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { HISTB_TIMER01_CLK, "clk_timer01", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) CLK_SET_RATE_PARENT, 0x48, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { HISTB_UART0_CLK, "clk_uart0", "75m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) CLK_SET_RATE_PARENT, 0x48, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = of_clk_add_provider(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) of_clk_src_onecell_get, &clk_data->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto unregister_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unregister_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .register_clks = hi3798cv200_sysctrl_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct of_device_id hi3798cv200_crg_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { .compatible = "hisilicon,hi3798cv200-crg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .data = &hi3798cv200_crg_funcs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { .compatible = "hisilicon,hi3798cv200-sysctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .data = &hi3798cv200_sysctrl_funcs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int hi3798cv200_crg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct hisi_crg_dev *crg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!crg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) crg->funcs = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!crg->funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) crg->rstc = hisi_reset_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!crg->rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) crg->clk_data = crg->funcs->register_clks(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (IS_ERR(crg->clk_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) hisi_reset_exit(crg->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return PTR_ERR(crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) platform_set_drvdata(pdev, crg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int hi3798cv200_crg_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) hisi_reset_exit(crg->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) crg->funcs->unregister_clks(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct platform_driver hi3798cv200_crg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .probe = hi3798cv200_crg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .remove = hi3798cv200_crg_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .name = "hi3798cv200-crg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .of_match_table = hi3798cv200_crg_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int __init hi3798cv200_crg_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return platform_driver_register(&hi3798cv200_crg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) core_initcall(hi3798cv200_crg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void __exit hi3798cv200_crg_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) platform_driver_unregister(&hi3798cv200_crg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) module_exit(hi3798cv200_crg_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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