^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hi3516CV300 Clock and Reset Generator Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <dt-bindings/clock/hi3516cv300-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "crg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* hi3516CV300 core CRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HI3516CV300_INNER_CLK_OFFSET 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HI3516CV300_FIXED_3M 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HI3516CV300_FIXED_6M 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HI3516CV300_FIXED_24M 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HI3516CV300_FIXED_49P5 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HI3516CV300_FIXED_50M 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HI3516CV300_FIXED_83P3M 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HI3516CV300_FIXED_99M 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HI3516CV300_FIXED_100M 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HI3516CV300_FIXED_148P5M 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HI3516CV300_FIXED_198M 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HI3516CV300_FIXED_297M 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HI3516CV300_UART_MUX 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HI3516CV300_FMC_MUX 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HI3516CV300_MMC0_MUX 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HI3516CV300_MMC1_MUX 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HI3516CV300_MMC2_MUX 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HI3516CV300_MMC3_MUX 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HI3516CV300_PWM_MUX 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HI3516CV300_CRG_NR_CLKS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct hisi_fixed_rate_clock hi3516cv300_fixed_rate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { HI3516CV300_APB_CLK, "apb", NULL, 0, 50000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const char *const uart_mux_p[] = {"24m", "6m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char *const fmc_mux_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "24m", "83.3m", "148.5m", "198m", "297m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const char *const mmc_mux_p[] = {"49.5m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const char *const mmc2_mux_p[] = {"99m", "49.5m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const char *const pwm_mux_p[] = {"3m", "50m", "24m", "24m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static u32 uart_mux_table[] = {0, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static u32 fmc_mux_table[] = {0, 1, 2, 3, 4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static u32 mmc_mux_table[] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static u32 mmc2_mux_table[] = {0, 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static u32 pwm_mux_table[] = {0, 1, 2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct hisi_mux_clock hi3516cv300_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { HI3516CV300_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { HI3516CV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { HI3516CV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { HI3516CV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { HI3516CV300_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { HI3516CV300_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { HI3516CV300_PWM_MUX, "pwm_mux", pwm_mux_p, ARRAY_SIZE(pwm_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0xe4, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0xe4, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0xe4, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0xe4, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0xe4, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0xc0, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { HI3516CV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0xc4, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { HI3516CV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0xc4, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { HI3516CV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0xc4, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { HI3516CV300_MMC3_CLK, "clk_mmc3", "mmc3_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0xc8, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { HI3516CV300_ETH_CLK, "clk_eth", NULL, 0, 0xec, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { HI3516CV300_DMAC_CLK, "clk_dmac", NULL, 0, 0xd8, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { HI3516CV300_PWM_CLK, "clk_pwm", "pwm_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x38, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { HI3516CV300_USB2_BUS_CLK, "clk_usb2_bus", NULL, 0, 0xb8, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { HI3516CV300_USB2_OHCI48M_CLK, "clk_usb2_ohci48m", NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0xb8, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { HI3516CV300_USB2_OHCI12M_CLK, "clk_usb2_ohci12m", NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0xb8, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { HI3516CV300_USB2_OTG_UTMI_CLK, "clk_usb2_otg_utmi", NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0xb8, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { HI3516CV300_USB2_HST_PHY_CLK, "clk_usb2_hst_phy", NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0xb8, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { HI3516CV300_USB2_UTMI0_CLK, "clk_usb2_utmi0", NULL, 0, 0xb8, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct hisi_clock_data *hi3516cv300_clk_register(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = hisi_clk_register_mux(hi3516cv300_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto unregister_fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = hisi_clk_register_gate(hi3516cv300_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) goto unregister_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = of_clk_add_provider(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) of_clk_src_onecell_get, &clk_data->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto unregister_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unregister_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) hisi_clk_unregister_gate(hi3516cv300_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unregister_mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) hisi_clk_unregister_mux(hi3516cv300_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unregister_fixed_rate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void hi3516cv300_clk_unregister(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) hisi_clk_unregister_gate(hi3516cv300_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) hisi_clk_unregister_mux(hi3516cv300_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct hisi_crg_funcs hi3516cv300_crg_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .register_clks = hi3516cv300_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .unregister_clks = hi3516cv300_clk_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* hi3516CV300 sysctrl CRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HI3516CV300_SYSCTRL_NR_CLKS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const char *const wdt_mux_p[] __initconst = { "3m", "apb" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static u32 wdt_mux_table[] = {0, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { HI3516CV300_WDT_CLK, "wdt", wdt_mux_p, ARRAY_SIZE(wdt_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = of_clk_add_provider(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) of_clk_src_onecell_get, &clk_data->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto unregister_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unregister_mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .register_clks = hi3516cv300_sysctrl_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .unregister_clks = hi3516cv300_sysctrl_clk_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct of_device_id hi3516cv300_crg_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .compatible = "hisilicon,hi3516cv300-crg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .data = &hi3516cv300_crg_funcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .compatible = "hisilicon,hi3516cv300-sysctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .data = &hi3516cv300_sysctrl_funcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int hi3516cv300_crg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct hisi_crg_dev *crg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!crg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) crg->funcs = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!crg->funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) crg->rstc = hisi_reset_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!crg->rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) crg->clk_data = crg->funcs->register_clks(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (IS_ERR(crg->clk_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) hisi_reset_exit(crg->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return PTR_ERR(crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) platform_set_drvdata(pdev, crg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int hi3516cv300_crg_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) hisi_reset_exit(crg->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) crg->funcs->unregister_clks(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct platform_driver hi3516cv300_crg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .probe = hi3516cv300_crg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .remove = hi3516cv300_crg_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .name = "hi3516cv300-crg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .of_match_table = hi3516cv300_crg_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int __init hi3516cv300_crg_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return platform_driver_register(&hi3516cv300_crg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) core_initcall(hi3516cv300_crg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void __exit hi3516cv300_crg_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) platform_driver_unregister(&hi3516cv300_crg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) module_exit(hi3516cv300_crg_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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