^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hisilicon clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012-2013 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2012-2013 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xin Li <li.xin@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static DEFINE_SPINLOCK(hisi_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int nr_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk **clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) clk_data = devm_kmalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) clk_data->base = devm_ioremap(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (!clk_data->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) clk_table = devm_kmalloc_array(&pdev->dev, nr_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) sizeof(*clk_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (!clk_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clk_data->clk_data.clks = clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) clk_data->clk_data.clk_num = nr_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) EXPORT_SYMBOL_GPL(hisi_clk_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct hisi_clock_data *hisi_clk_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int nr_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk **clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pr_err("%s: failed to map clock registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) clk_data->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (!clk_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) goto err_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clk_data->clk_data.clks = clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk_data->clk_data.clk_num = nr_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) err_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) EXPORT_SYMBOL_GPL(hisi_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int nums, struct hisi_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clk = clk_register_fixed_rate(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clks[i].fixed_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int nums,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct hisi_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk = clk_register_fixed_factor(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clks[i].flags, clks[i].mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clks[i].div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clk_unregister_fixed_factor(data->clk_data.clks[clks[i].id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int hisi_clk_register_mux(const struct hisi_mux_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int nums, struct hisi_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 mask = BIT(clks[i].width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk = clk_register_mux_table(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clks[i].parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clks[i].num_parents, clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) base + clks[i].offset, clks[i].shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mask, clks[i].mux_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clks[i].table, &hisi_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (clks[i].alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clk_register_clkdev(clk, clks[i].alias, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clk_unregister_mux(data->clk_data.clks[clks[i].id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) EXPORT_SYMBOL_GPL(hisi_clk_register_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int hisi_clk_register_phase(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) const struct hisi_phase_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int nums, struct hisi_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk = clk_register_hisi_phase(dev, &clks[i], base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) &hisi_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pr_err("%s: failed to register clock %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EXPORT_SYMBOL_GPL(hisi_clk_register_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int hisi_clk_register_divider(const struct hisi_divider_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int nums, struct hisi_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) clk = clk_register_divider_table(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) base + clks[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) clks[i].shift, clks[i].width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clks[i].div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) clks[i].table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) &hisi_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (clks[i].alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) clk_register_clkdev(clk, clks[i].alias, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clk_unregister_divider(data->clk_data.clks[clks[i].id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EXPORT_SYMBOL_GPL(hisi_clk_register_divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int hisi_clk_register_gate(const struct hisi_gate_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int nums, struct hisi_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) clk = clk_register_gate(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) base + clks[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clks[i].bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clks[i].gate_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) &hisi_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (clks[i].alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk_register_clkdev(clk, clks[i].alias, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk_unregister_gate(data->clk_data.clks[clks[i].id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) EXPORT_SYMBOL_GPL(hisi_clk_register_gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int nums, struct hisi_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) clk = hisi_register_clkgate_sep(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) base + clks[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clks[i].bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) clks[i].gate_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) &hisi_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (clks[i].alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk_register_clkdev(clk, clks[i].alias, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) EXPORT_SYMBOL_GPL(hisi_clk_register_gate_sep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int nums, struct hisi_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk = hi6220_register_clkdiv(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) base + clks[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) clks[i].shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) clks[i].width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) clks[i].mask_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &hisi_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (clks[i].alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) clk_register_clkdev(clk, clks[i].alias, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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