^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <dt-bindings/clock/hix5hd2-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) { HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) { HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) { HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) { HIX5HD2_FIXED_24M, "24m", NULL, 0, 24000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) { HIX5HD2_FIXED_600M, "600m", NULL, 0, 600000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) { HIX5HD2_FIXED_300M, "300m", NULL, 0, 300000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) { HIX5HD2_FIXED_75M, "75m", NULL, 0, 75000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { HIX5HD2_FIXED_200M, "200m", NULL, 0, 200000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { HIX5HD2_FIXED_100M, "100m", NULL, 0, 100000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { HIX5HD2_FIXED_40M, "40m", NULL, 0, 40000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { HIX5HD2_FIXED_150M, "150m", NULL, 0, 150000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { HIX5HD2_FIXED_1728M, "1728m", NULL, 0, 1728000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { HIX5HD2_FIXED_28P8M, "28p8m", NULL, 0, 28000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { HIX5HD2_FIXED_432M, "432m", NULL, 0, 432000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { HIX5HD2_FIXED_345P6M, "345p6m", NULL, 0, 345000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { HIX5HD2_FIXED_288M, "288m", NULL, 0, 288000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { HIX5HD2_FIXED_60M, "60m", NULL, 0, 60000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { HIX5HD2_FIXED_750M, "750m", NULL, 0, 750000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { HIX5HD2_FIXED_500M, "500m", NULL, 0, 500000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { HIX5HD2_FIXED_54M, "54m", NULL, 0, 54000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { HIX5HD2_FIXED_27M, "27m", NULL, 0, 27000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { HIX5HD2_FIXED_1500M, "1500m", NULL, 0, 1500000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { HIX5HD2_FIXED_375M, "375m", NULL, 0, 375000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { HIX5HD2_FIXED_187M, "187m", NULL, 0, 187000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { HIX5HD2_FIXED_250M, "250m", NULL, 0, 250000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { HIX5HD2_FIXED_125M, "125m", NULL, 0, 125000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { HIX5HD2_FIXED_2P02M, "2m", NULL, 0, 2000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { HIX5HD2_FIXED_50M, "50m", NULL, 0, 50000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { HIX5HD2_FIXED_25M, "25m", NULL, 0, 25000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char *const sfc_mux_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "24m", "150m", "200m", "100m", "75m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const char *const sdio_mux_p[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "75m", "100m", "50m", "15m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static u32 sdio_mux_table[] = {0, 1, 2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const char *const fephy_mux_p[] __initconst = { "25m", "125m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static u32 fephy_mux_table[] = {0, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { HIX5HD2_SD_MUX, "sd_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { HIX5HD2_FEPHY_MUX, "fephy_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) fephy_mux_p, ARRAY_SIZE(fephy_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* sfc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { HIX5HD2_SFC_RST, "rst_sfc", "clk_sfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* sdio0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { HIX5HD2_SD_BIU_CLK, "clk_sd_biu", "200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { HIX5HD2_SD_CIU_CLK, "clk_sd_ciu", "sd_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { HIX5HD2_SD_CIU_RST, "rst_sd_ciu", "clk_sd_ciu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* sdio1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { HIX5HD2_MMC_BIU_CLK, "clk_mmc_biu", "200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { HIX5HD2_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* gsf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { HIX5HD2_FWD_BUS_CLK, "clk_fwd_bus", NULL, 0, 0xcc, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CLK_SET_RATE_PARENT, 0x120, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* wdg0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { HIX5HD2_WDG0_CLK, "clk_wdg0", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CLK_SET_RATE_PARENT, 0x178, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { HIX5HD2_WDG0_RST, "rst_wdg0", "clk_wdg0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {HIX5HD2_I2C0_CLK, "clk_i2c0", "100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) CLK_SET_RATE_PARENT, 0x06c, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {HIX5HD2_I2C0_RST, "rst_i2c0", "clk_i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CLK_SET_RATE_PARENT, 0x06c, 5, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {HIX5HD2_I2C1_CLK, "clk_i2c1", "100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CLK_SET_RATE_PARENT, 0x06c, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {HIX5HD2_I2C1_RST, "rst_i2c1", "clk_i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CLK_SET_RATE_PARENT, 0x06c, 9, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {HIX5HD2_I2C2_CLK, "clk_i2c2", "100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CLK_SET_RATE_PARENT, 0x06c, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {HIX5HD2_I2C2_RST, "rst_i2c2", "clk_i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CLK_SET_RATE_PARENT, 0x06c, 13, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {HIX5HD2_I2C3_CLK, "clk_i2c3", "100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CLK_SET_RATE_PARENT, 0x06c, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {HIX5HD2_I2C3_RST, "rst_i2c3", "clk_i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) CLK_SET_RATE_PARENT, 0x06c, 17, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {HIX5HD2_I2C4_CLK, "clk_i2c4", "100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) CLK_SET_RATE_PARENT, 0x06c, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {HIX5HD2_I2C4_RST, "rst_i2c4", "clk_i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CLK_SET_RATE_PARENT, 0x06c, 21, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {HIX5HD2_I2C5_CLK, "clk_i2c5", "100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CLK_SET_RATE_PARENT, 0x06c, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {HIX5HD2_I2C5_RST, "rst_i2c5", "clk_i2c5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CLK_SET_RATE_PARENT, 0x06c, 1, CLK_GATE_SET_TO_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum hix5hd2_clk_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) TYPE_COMPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) TYPE_ETHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct hix5hd2_complex_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 ctrl_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 ctrl_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 phy_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 phy_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum hix5hd2_clk_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct hix5hd2_clk_complex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 ctrl_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 ctrl_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void __iomem *phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 phy_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 phy_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0xcc, 0x14, 0xa00, 0x168, 0x2, 0, TYPE_ETHER},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {"clk_sata", NULL, HIX5HD2_SATA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 0xa8, 0x1f, 0x300, 0xac, 0x1, 0x0, TYPE_COMPLEX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {"clk_usb", NULL, HIX5HD2_USB_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0xb8, 0xff, 0x3f000, 0xbc, 0x7, 0x3f00, TYPE_COMPLEX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define to_complex_clk(_hw) container_of(_hw, struct hix5hd2_clk_complex, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int clk_ether_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) val = readl_relaxed(clk->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel_relaxed(val, clk->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) val &= ~(clk->ctrl_rst_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel_relaxed(val, clk->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val = readl_relaxed(clk->phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) val |= clk->phy_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) val &= ~(clk->phy_rst_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel_relaxed(val, clk->phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) val &= ~(clk->phy_clk_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= clk->phy_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel_relaxed(val, clk->phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val |= clk->phy_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val &= ~(clk->phy_rst_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel_relaxed(val, clk->phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mdelay(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void clk_ether_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) val = readl_relaxed(clk->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) val &= ~(clk->ctrl_clk_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) writel_relaxed(val, clk->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct clk_ops clk_ether_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .prepare = clk_ether_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .unprepare = clk_ether_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int clk_complex_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) val = readl_relaxed(clk->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val |= clk->ctrl_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val &= ~(clk->ctrl_rst_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel_relaxed(val, clk->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) val = readl_relaxed(clk->phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val |= clk->phy_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) val &= ~(clk->phy_rst_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel_relaxed(val, clk->phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void clk_complex_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val = readl_relaxed(clk->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val |= clk->ctrl_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val &= ~(clk->ctrl_clk_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel_relaxed(val, clk->ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) val = readl_relaxed(clk->phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val |= clk->phy_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val &= ~(clk->phy_clk_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel_relaxed(val, clk->phy_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct clk_ops clk_complex_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .enable = clk_complex_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .disable = clk_complex_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct hisi_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 0; i < nums; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct hix5hd2_clk_complex *p_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!p_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) init.name = clks[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (clks[i].type == TYPE_ETHER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) init.ops = &clk_ether_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) init.ops = &clk_complex_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) init.parent_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) (clks[i].parent_name ? &clks[i].parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) init.num_parents = (clks[i].parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) p_clk->ctrl_reg = base + clks[i].ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) p_clk->ctrl_clk_mask = clks[i].ctrl_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) p_clk->ctrl_rst_mask = clks[i].ctrl_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) p_clk->phy_reg = base + clks[i].phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) p_clk->phy_clk_mask = clks[i].phy_clk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) p_clk->phy_rst_mask = clks[i].phy_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) p_clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk = clk_register(NULL, &p_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) kfree(p_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) data->clk_data.clks[clks[i].id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void __init hix5hd2_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ARRAY_SIZE(hix5hd2_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) hisi_clk_register_gate(hix5hd2_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ARRAY_SIZE(hix5hd2_gate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) hix5hd2_clk_register_complex(hix5hd2_complex_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ARRAY_SIZE(hix5hd2_complex_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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