^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Simple HiSilicon phase clock implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct clk_hisi_phase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 *phase_degrees;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 *phase_regvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 phase_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define to_clk_hisi_phase(_hw) container_of(_hw, struct clk_hisi_phase, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) for (i = 0; i < phase->phase_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (phase->phase_regvals[i] == regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return phase->phase_degrees[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int hisi_clk_get_phase(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) regval = readl(phase->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) regval = (regval & phase->mask) >> phase->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return hisi_phase_regval_to_degrees(phase, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) for (i = 0; i < phase->phase_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (phase->phase_degrees[i] == degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return phase->phase_regvals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int hisi_clk_set_phase(struct clk_hw *hw, int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) regval = hisi_phase_degrees_to_regval(phase, degrees);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (regval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) spin_lock_irqsave(phase->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) val = readl(phase->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) val &= ~phase->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val |= regval << phase->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel(val, phase->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) spin_unlock_irqrestore(phase->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct clk_ops clk_phase_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .get_phase = hisi_clk_get_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .set_phase = hisi_clk_set_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *clk_register_hisi_phase(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct hisi_phase_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *base, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct clk_hisi_phase *phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) phase = devm_kzalloc(dev, sizeof(struct clk_hisi_phase), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!phase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) init.name = clks->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) init.ops = &clk_phase_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) init.flags = clks->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) init.parent_names = clks->parent_names ? &clks->parent_names : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) init.num_parents = clks->parent_names ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) phase->reg = base + clks->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) phase->shift = clks->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) phase->mask = (BIT(clks->width) - 1) << clks->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) phase->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) phase->phase_degrees = clks->phase_degrees;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) phase->phase_regvals = clks->phase_regvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) phase->phase_num = clks->phase_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) phase->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return devm_clk_register(dev, &phase->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EXPORT_SYMBOL_GPL(clk_register_hisi_phase);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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