Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Hisilicon HiP04 clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2013-2014 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (c) 2013-2014 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/hip04-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	{ HIP04_OSC50M,   "osc50m",   NULL, 0, 50000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	{ HIP04_CLK_50M,  "clk50m",   NULL, 0, 50000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	{ HIP04_CLK_168M, "clk168m",  NULL, 0, 168750000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void __init hip04_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	clk_data = hisi_clk_init(np, HIP04_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				     ARRAY_SIZE(hip04_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 				     clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);