^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hisilicon Hi6220 clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Bintian Wang <bintian.wang@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/hi6220-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* clocks in AO (always on) controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { HI6220_REF32K, "ref32k", NULL, 0, 32764, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { HI6220_CLK_TCXO, "clk_tcxo", NULL, 0, 19200000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { HI6220_MMC1_PAD, "mmc1_pad", NULL, 0, 100000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { HI6220_MMC2_PAD, "mmc2_pad", NULL, 0, 100000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { HI6220_MMC0_PAD, "mmc0_pad", NULL, 0, 200000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { HI6220_PLL_SYS, "syspll", NULL, 0, 1190400000,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { HI6220_DDR_SRC, "ddr_sel_src", NULL, 0, 1200000000,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { HI6220_PLL_MEDIA, "media_pll", NULL, 0, 1440000000,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { HI6220_PLL_DDR, "ddrpll0", NULL, 0, 1600000000,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { HI6220_300M, "clk_300m", "syspll", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { HI6220_150M, "clk_150m", "clk_300m", 1, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { HI6220_PICOPHY_SRC, "picophy_src", "clk_150m", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { HI6220_MMC0_SRC_SEL, "mmc0srcsel", "mmc0_sel", 1, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { HI6220_MMC1_SRC_SEL, "mmc1srcsel", "mmc1_sel", 1, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { HI6220_MMC2_SRC_SEL, "mmc2srcsel", "mmc2_sel", 1, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { HI6220_VPU_CODEC, "vpucodec", "codec_jpeg_aclk", 1, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { HI6220_MMC0_SMP, "mmc0_sample", "mmc0_sel", 1, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { HI6220_MMC1_SMP, "mmc1_sample", "mmc1_sel", 1, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { HI6220_MMC2_SMP, "mmc2_sample", "mmc2_sel", 1, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { HI6220_RTC0_PCLK, "rtc0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { HI6220_RTC1_PCLK, "rtc1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void __init hi6220_clk_ao_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct hisi_clock_data *clk_data_ao;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (!clk_data_ao)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Allow reset driver to probe as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* clocks in sysctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char *mmc0_mux1_p[] __initdata = { "mmc0_mux0", "pll_media_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const char *mmc0_src_p[] __initdata = { "mmc0srcsel", "mmc0_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char *mmc1_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char *mmc1_mux1_p[] __initdata = { "mmc1_mux0", "pll_media_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const char *mmc1_src_p[] __initdata = { "mmc1srcsel", "mmc1_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char *mmc2_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char *mmc2_mux1_p[] __initdata = { "mmc2_mux0", "pll_media_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char *mmc2_src_p[] __initdata = { "mmc2srcsel", "mmc2_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char *mmc0_sample_in[] __initdata = { "mmc0_sample", "mmc0_pad", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char *mmc1_sample_in[] __initdata = { "mmc1_sample", "mmc1_pad", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const char *mmc2_sample_in[] __initdata = { "mmc2_sample", "mmc2_pad", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const char *uart1_src[] __initdata = { "clk_tcxo", "clk_150m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const char *uart2_src[] __initdata = { "clk_tcxo", "clk_150m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const char *uart3_src[] __initdata = { "clk_tcxo", "clk_150m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { HI6220_MMC0_CLK, "mmc0_clk", "mmc0_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { HI6220_MMC0_CIUCLK, "mmc0_ciuclk", "mmc0_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { HI6220_MMC1_CLK, "mmc1_clk", "mmc1_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { HI6220_MMC1_CIUCLK, "mmc1_ciuclk", "mmc1_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { HI6220_MMC2_CLK, "mmc2_clk", "mmc2_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { HI6220_MMC2_CIUCLK, "mmc2_ciuclk", "mmc2_smp_in", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { HI6220_USBOTG_HCLK, "usbotg_hclk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { HI6220_CLK_PICOPHY, "clk_picophy", "cs_dapb", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { HI6220_HIFI, "hifi_clk", "hifi_div", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x210, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { HI6220_DACODEC_PCLK, "dacodec_pclk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x210, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { HI6220_EDMAC_ACLK, "edmac_aclk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x220, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { HI6220_CS_ATB, "cs_atb", "cs_atb_div", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { HI6220_I2C0_CLK, "i2c0_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { HI6220_I2C1_CLK, "i2c1_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { HI6220_I2C2_CLK, "i2c2_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { HI6220_I2C3_CLK, "i2c3_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { HI6220_UART1_PCLK, "uart1_pclk", "uart1_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { HI6220_UART2_PCLK, "uart2_pclk", "uart2_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { HI6220_UART3_PCLK, "uart3_pclk", "uart3_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { HI6220_UART4_PCLK, "uart4_pclk", "uart4_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { HI6220_SPI_CLK, "spi_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { HI6220_TSENSOR_CLK, "tsensor_clk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { HI6220_DAPB_CLK, "dapb_clk", "cs_dapb", CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x230, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { HI6220_MMU_CLK, "mmu_clk", "ddrc_axi1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x240, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { HI6220_HIFI_SEL, "hifi_sel", "hifi_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { HI6220_MMC0_SYSPLL, "mmc0_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { HI6220_MMC1_SYSPLL, "mmc1_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { HI6220_MMC2_SYSPLL, "mmc2_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { HI6220_MMC0_SEL, "mmc0_sel", "mmc0_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { HI6220_MMC1_SEL, "mmc1_sel", "mmc1_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { HI6220_BBPPLL_SEL, "bbppll_sel", "pll0_bbp_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { HI6220_MMC2_SEL, "mmc2_sel", "mmc2_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x270, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { HI6220_MMC0_SRC, "mmc0_src", mmc0_src_p, ARRAY_SIZE(mmc0_src_p), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { HI6220_MMC0_SMP_IN, "mmc0_smp_in", mmc0_sample_in, ARRAY_SIZE(mmc0_sample_in), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { HI6220_MMC1_SRC, "mmc1_src", mmc1_src_p, ARRAY_SIZE(mmc1_src_p), CLK_SET_RATE_PARENT, 0x4, 2, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { HI6220_MMC1_SMP_IN, "mmc1_smp_in", mmc1_sample_in, ARRAY_SIZE(mmc1_sample_in), CLK_SET_RATE_PARENT, 0x4, 2, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { HI6220_MMC2_SRC, "mmc2_src", mmc2_src_p, ARRAY_SIZE(mmc2_src_p), CLK_SET_RATE_PARENT, 0x4, 4, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { HI6220_MMC2_SMP_IN, "mmc2_smp_in", mmc2_sample_in, ARRAY_SIZE(mmc2_sample_in), CLK_SET_RATE_PARENT, 0x4, 4, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { HI6220_HIFI_SRC, "hifi_src", hifi_src, ARRAY_SIZE(hifi_src), CLK_SET_RATE_PARENT, 0x400, 0, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { HI6220_UART1_SRC, "uart1_src", uart1_src, ARRAY_SIZE(uart1_src), CLK_SET_RATE_PARENT, 0x400, 1, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { HI6220_UART2_SRC, "uart2_src", uart2_src, ARRAY_SIZE(uart2_src), CLK_SET_RATE_PARENT, 0x400, 2, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { HI6220_UART3_SRC, "uart3_src", uart3_src, ARRAY_SIZE(uart3_src), CLK_SET_RATE_PARENT, 0x400, 3, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { HI6220_UART4_SRC, "uart4_src", uart4_src, ARRAY_SIZE(uart4_src), CLK_SET_RATE_PARENT, 0x400, 4, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { HI6220_MMC0_MUX0, "mmc0_mux0", mmc0_mux0_p, ARRAY_SIZE(mmc0_mux0_p), CLK_SET_RATE_PARENT, 0x400, 5, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { HI6220_MMC1_MUX0, "mmc1_mux0", mmc1_mux0_p, ARRAY_SIZE(mmc1_mux0_p), CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { HI6220_MMC2_MUX0, "mmc2_mux0", mmc2_mux0_p, ARRAY_SIZE(mmc2_mux0_p), CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { HI6220_MMC0_MUX1, "mmc0_mux1", mmc0_mux1_p, ARRAY_SIZE(mmc0_mux1_p), CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { HI6220_MMC1_MUX1, "mmc1_mux1", mmc1_mux1_p, ARRAY_SIZE(mmc1_mux1_p), CLK_SET_RATE_PARENT, 0x400, 14, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { HI6220_MMC2_MUX1, "mmc2_mux1", mmc2_mux1_p, ARRAY_SIZE(mmc2_mux1_p), CLK_SET_RATE_PARENT, 0x400, 15, 1, CLK_MUX_HIWORD_MASK,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { HI6220_CLK_BUS, "clk_bus", "clk_300m", CLK_SET_RATE_PARENT, 0x490, 0, 4, 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { HI6220_MMC0_DIV, "mmc0_div", "mmc0_syspll", CLK_SET_RATE_PARENT, 0x494, 0, 6, 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { HI6220_MMC1_DIV, "mmc1_div", "mmc1_syspll", CLK_SET_RATE_PARENT, 0x498, 0, 6, 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { HI6220_MMC2_DIV, "mmc2_div", "mmc2_syspll", CLK_SET_RATE_PARENT, 0x49c, 0, 6, 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { HI6220_HIFI_DIV, "hifi_div", "hifi_sel", CLK_SET_RATE_PARENT, 0x4a0, 0, 4, 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { HI6220_BBPPLL0_DIV, "bbppll0_div", "bbppll_sel", CLK_SET_RATE_PARENT, 0x4a0, 8, 6, 15,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { HI6220_CS_DAPB, "cs_dapb", "picophy_src", CLK_SET_RATE_PARENT, 0x4a0, 24, 2, 31,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { HI6220_CS_ATB_DIV, "cs_atb_div", "cs_atb_syspll", CLK_SET_RATE_PARENT, 0x4a4, 0, 4, 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void __init hi6220_clk_sys_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) hisi_clk_register_mux(hi6220_mux_clks_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) hi6220_clk_register_divider(hi6220_div_clks_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* clocks in media controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char *clk_1000_1200_src[] __initdata = { "pll_gpu_gate", "media_syspll_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const char *clk_1440_1200_src[] __initdata = { "media_syspll_src", "media_pll_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const char *clk_1000_1440_src[] __initdata = { "pll_gpu_gate", "media_pll_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { HI6220_DSI_PCLK, "dsi_pclk", "vpucodec", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { HI6220_G3D_PCLK, "g3d_pclk", "vpucodec", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { HI6220_ACLK_CODEC_VPU, "aclk_codec_vpu", "ade_core_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { HI6220_ISP_SCLK, "isp_sclk", "isp_sclk_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { HI6220_ADE_CORE, "ade_core", "ade_core_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { HI6220_MED_MMU, "media_mmu", "mmu_clk", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { HI6220_CFG_CSI4PHY, "cfg_csi4phy", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { HI6220_CFG_CSI2PHY, "cfg_csi2phy", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { HI6220_ISP_SCLK_GATE, "isp_sclk_gate", "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { HI6220_ISP_SCLK_GATE1, "isp_sclk_gate1", "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { HI6220_ADE_CORE_GATE, "ade_core_gate", "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { HI6220_CODEC_VPU_GATE, "codec_vpu_gate", "clk_1000_1440", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { HI6220_MED_SYSPLL, "media_syspll_src", "media_syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct hisi_mux_clock hi6220_mux_clks_media[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { HI6220_1440_1200, "clk_1440_1200", clk_1440_1200_src, ARRAY_SIZE(clk_1440_1200_src), CLK_SET_RATE_PARENT, 0x51c, 0, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { HI6220_1000_1200, "clk_1000_1200", clk_1000_1200_src, ARRAY_SIZE(clk_1000_1200_src), CLK_SET_RATE_PARENT, 0x51c, 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { HI6220_1000_1440, "clk_1000_1440", clk_1000_1440_src, ARRAY_SIZE(clk_1000_1440_src), CLK_SET_RATE_PARENT, 0x51c, 6, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { HI6220_CODEC_JPEG, "codec_jpeg_aclk", "media_pll_src", CLK_SET_RATE_PARENT, 0xcbc, 0, 4, 23, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { HI6220_ISP_SCLK_SRC, "isp_sclk_src", "isp_sclk_gate", CLK_SET_RATE_PARENT, 0xcbc, 8, 4, 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { HI6220_ISP_SCLK1, "isp_sclk1", "isp_sclk_gate1", CLK_SET_RATE_PARENT, 0xcbc, 24, 4, 31, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { HI6220_ADE_CORE_SRC, "ade_core_src", "ade_core_gate", CLK_SET_RATE_PARENT, 0xcc0, 16, 3, 23, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { HI6220_ADE_PIX_SRC, "ade_pix_src", "clk_1440_1200", CLK_SET_RATE_PARENT, 0xcc0, 24, 6, 31, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { HI6220_G3D_CLK, "g3d_clk", "clk_1000_1200", CLK_SET_RATE_PARENT, 0xcc4, 8, 4, 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { HI6220_CODEC_VPU_SRC, "codec_vpu_src", "codec_vpu_gate", CLK_SET_RATE_PARENT, 0xcc4, 24, 6, 31, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void __init hi6220_clk_media_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) clk_data = hisi_clk_init(np, HI6220_MEDIA_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) hisi_clk_register_mux(hi6220_mux_clks_media,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ARRAY_SIZE(hi6220_mux_clks_media), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) hi6220_clk_register_divider(hi6220_div_clks_media,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ARRAY_SIZE(hi6220_div_clks_media), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* clocks in pmctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { HI6220_PLL_GPU_GATE, "pll_gpu_gate", "gpupll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x8, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { HI6220_PLL1_DDR_GATE, "pll1_ddr_gate", "ddrpll1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x10, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { HI6220_PLL_DDR_GATE, "pll_ddr_gate", "ddrpll0", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x18, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { HI6220_PLL_MEDIA_GATE, "pll_media_gate", "media_pll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x38, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { HI6220_PLL0_BBP_GATE, "pll0_bbp_gate", "bbppll0", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x48, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { HI6220_DDRC_SRC, "ddrc_src", "ddr_sel_src", CLK_SET_RATE_PARENT, 0x5a8, 0, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { HI6220_DDRC_AXI1, "ddrc_axi1", "ddrc_src", CLK_SET_RATE_PARENT, 0x5a8, 8, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void __init hi6220_clk_power_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) hisi_clk_register_gate(hi6220_gate_clks_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ARRAY_SIZE(hi6220_gate_clks_power), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) hi6220_clk_register_divider(hi6220_div_clks_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ARRAY_SIZE(hi6220_div_clks_power), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* clocks in acpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { HI6220_ACPU_SFT_AT_S, "sft_at_s", "cs_atb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void __init hi6220_clk_acpu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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