^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hi6220 stub clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2015 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Leo Yan <leo.yan@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mailbox_client.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Stub clocks id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HI6220_STUB_ACPU0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HI6220_STUB_ACPU1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HI6220_STUB_GPU 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HI6220_STUB_DDR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Mailbox message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HI6220_MBOX_MSG_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HI6220_MBOX_FREQ 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HI6220_MBOX_CMD_SET 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HI6220_MBOX_OBJ_AP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* CPU dynamic frequency scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ACPU_DFS_FREQ_MAX 0x1724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ACPU_DFS_CUR_FREQ 0x17CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ACPU_DFS_FLAG 0x1B30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ACPU_DFS_FREQ_REQ 0x1B34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ACPU_DFS_FREQ_LMT 0x1B38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ACPU_DFS_LOCK_FLAG 0xAEAEAEAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define to_stub_clk(hw) container_of(hw, struct hi6220_stub_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct hi6220_stub_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct regmap *dfs_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct mbox_client cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mbox_chan *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct hi6220_mbox_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned char type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned char obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned char src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned char para[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) union hi6220_mbox_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int data[HI6220_MBOX_MSG_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct hi6220_mbox_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static unsigned int hi6220_acpu_get_freq(struct hi6220_stub_clk *stub_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int hi6220_acpu_set_freq(struct hi6220_stub_clk *stub_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) union hi6220_mbox_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* set the frequency in sram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* compound mailbox message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) data.msg.type = HI6220_MBOX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) data.msg.cmd = HI6220_MBOX_CMD_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) data.msg.obj = HI6220_MBOX_OBJ_AP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) data.msg.src = HI6220_MBOX_OBJ_AP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mbox_send_message(stub_clk->mbox, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int hi6220_acpu_round_freq(struct hi6220_stub_clk *stub_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int limit_flag, limit_freq = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* check the constrained frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (limit_flag == ACPU_DFS_LOCK_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* check the supported maximum frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_MAX, &max_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* calculate the real maximum frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) max_freq = min(max_freq, limit_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (WARN_ON(freq > max_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) freq = max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static unsigned long hi6220_stub_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) switch (stub_clk->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case HI6220_STUB_ACPU0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rate = hi6220_acpu_get_freq(stub_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* convert from kHz to Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) rate *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __func__, stub_clk->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int hi6220_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long new_rate = rate / 1000; /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) switch (stub_clk->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case HI6220_STUB_ACPU0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = hi6220_acpu_set_freq(stub_clk, new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __func__, stub_clk->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pr_debug("%s: set rate=%ldkHz\n", __func__, new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static long hi6220_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long new_rate = rate / 1000; /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) switch (stub_clk->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case HI6220_STUB_ACPU0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) new_rate = hi6220_acpu_round_freq(stub_clk, new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* convert from kHz to Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) new_rate *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __func__, stub_clk->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct clk_ops hi6220_stub_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .recalc_rate = hi6220_stub_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .round_rate = hi6220_stub_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .set_rate = hi6220_stub_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int hi6220_stub_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct hi6220_stub_clk *stub_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) stub_clk = devm_kzalloc(dev, sizeof(*stub_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!stub_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) stub_clk->dfs_map = syscon_regmap_lookup_by_phandle(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "hisilicon,hi6220-clk-sram");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(stub_clk->dfs_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_err(dev, "failed to get sram regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return PTR_ERR(stub_clk->dfs_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) stub_clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) stub_clk->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) stub_clk->id = HI6220_STUB_ACPU0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Use mailbox client with blocking mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) stub_clk->cl.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) stub_clk->cl.tx_done = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) stub_clk->cl.tx_block = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) stub_clk->cl.tx_tout = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) stub_clk->cl.knows_txdone = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Allocate mailbox channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) stub_clk->mbox = mbox_request_channel(&stub_clk->cl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(stub_clk->mbox)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(dev, "failed get mailbox channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return PTR_ERR(stub_clk->mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) init.name = "acpu0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) init.ops = &hi6220_stub_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk = devm_clk_register(dev, &stub_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(dev, "failed to register OF clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* initialize buffer to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) regmap_write(stub_clk->dfs_map, ACPU_DFS_FLAG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_dbg(dev, "Registered clock '%s'\n", init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct of_device_id hi6220_stub_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { .compatible = "hisilicon,hi6220-stub-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct platform_driver hi6220_stub_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "hi6220-stub-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .of_match_table = hi6220_stub_clk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .probe = hi6220_stub_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int __init hi6220_stub_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return platform_driver_register(&hi6220_stub_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) subsys_initcall(hi6220_stub_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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