^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: chenjun <chenjun14@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2018, Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/hi3670-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const struct hisi_fixed_rate_clock hi3670_fixed_rate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) { HI3670_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) { HI3670_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) { HI3670_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 134400000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) { HI3670_CLK_PPLL0, "clk_ppll0", NULL, 0, 1660000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { HI3670_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { HI3670_CLK_PPLL2, "clk_ppll2", NULL, 0, 1920000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { HI3670_CLK_PPLL3, "clk_ppll3", NULL, 0, 1200000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { HI3670_CLK_PPLL4, "clk_ppll4", NULL, 0, 900000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { HI3670_CLK_PPLL6, "clk_ppll6", NULL, 0, 393216000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { HI3670_CLK_PPLL7, "clk_ppll7", NULL, 0, 1008000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { HI3670_CLK_PPLL_PCIE, "clk_ppll_pcie", NULL, 0, 100000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { HI3670_CLK_PCIEPLL_REV, "clk_pciepll_rev", NULL, 0, 100000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { HI3670_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { HI3670_PCLK, "pclk", NULL, 0, 20000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { HI3670_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { HI3670_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { HI3670_OSC32K, "osc32k", NULL, 0, 32764, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { HI3670_OSC19M, "osc19m", NULL, 0, 19200000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { HI3670_CLK_480M, "clk_480m", NULL, 0, 480000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { HI3670_CLK_INVALID, "clk_invalid", NULL, 0, 10000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* crgctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const struct hisi_fixed_factor_clock hi3670_crg_fixed_factor_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { HI3670_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 1, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { HI3670_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 1, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { HI3670_CLK_SD_SYS, "clk_sd_sys", "clk_sd_sys_gt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 1, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { HI3670_CLK_SDIO_SYS, "clk_sdio_sys", "clk_sdio_sys_gt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 1, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { HI3670_CLK_DIV_A53HPM, "clk_div_a53hpm", "clk_a53hpm_andgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { HI3670_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 1, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { HI3670_PCLK_GATE_UART0, "pclk_gate_uart0", "clk_mux_uartl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { HI3670_CLK_FACTOR_UART0, "clk_factor_uart0", "clk_mux_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { HI3670_CLK_FACTOR_USB3PHY_PLL, "clk_factor_usb3phy_pll", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 1, 60, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { HI3670_CLK_GATE_ABB_USB, "clk_gate_abb_usb", "clk_gate_usb_tcxo_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { HI3670_CLK_GATE_UFSPHY_REF, "clk_gate_ufsphy_ref", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { HI3670_ICS_VOLT_HIGH, "ics_volt_high", "peri_volt_hold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { HI3670_ICS_VOLT_MIDDLE, "ics_volt_middle", "peri_volt_middle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { HI3670_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { HI3670_VDEC_VOLT_HOLD, "vdec_volt_hold", "peri_volt_hold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { HI3670_EDC_VOLT_HOLD, "edc_volt_hold", "peri_volt_hold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { HI3670_CLK_ISP_SNCLK_FAC, "clk_isp_snclk_fac", "clk_isp_snclk_angt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 1, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { HI3670_CLK_FACTOR_RXDPHY, "clk_factor_rxdphy", "clk_andgt_rxdphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 1, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { HI3670_PPLL1_EN_ACPU, "ppll1_en_acpu", "clk_ppll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CLK_SET_RATE_PARENT, 0x0, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { HI3670_PPLL2_EN_ACPU, "ppll2_en_acpu", "clk_ppll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CLK_SET_RATE_PARENT, 0x0, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { HI3670_PPLL3_EN_ACPU, "ppll3_en_acpu", "clk_ppll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CLK_SET_RATE_PARENT, 0x0, 27, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { HI3670_PPLL1_GT_CPU, "ppll1_gt_cpu", "clk_ppll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CLK_SET_RATE_PARENT, 0x460, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { HI3670_PPLL2_GT_CPU, "ppll2_gt_cpu", "clk_ppll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CLK_SET_RATE_PARENT, 0x460, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { HI3670_PPLL3_GT_CPU, "ppll3_gt_cpu", "clk_ppll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CLK_SET_RATE_PARENT, 0x460, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { HI3670_CLK_GATE_PPLL2_MEDIA, "clk_gate_ppll2_media", "clk_ppll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CLK_SET_RATE_PARENT, 0x410, 27, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { HI3670_CLK_GATE_PPLL3_MEDIA, "clk_gate_ppll3_media", "clk_ppll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CLK_SET_RATE_PARENT, 0x410, 28, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { HI3670_CLK_GATE_PPLL4_MEDIA, "clk_gate_ppll4_media", "clk_ppll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CLK_SET_RATE_PARENT, 0x410, 26, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { HI3670_CLK_GATE_PPLL6_MEDIA, "clk_gate_ppll6_media", "clk_ppll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CLK_SET_RATE_PARENT, 0x410, 30, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { HI3670_CLK_GATE_PPLL7_MEDIA, "clk_gate_ppll7_media", "clk_ppll7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) CLK_SET_RATE_PARENT, 0x410, 29, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { HI3670_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CLK_SET_RATE_PARENT, 0x10, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { HI3670_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CLK_SET_RATE_PARENT, 0x10, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { HI3670_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CLK_SET_RATE_PARENT, 0x10, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { HI3670_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CLK_SET_RATE_PARENT, 0x10, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { HI3670_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CLK_SET_RATE_PARENT, 0x10, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { HI3670_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CLK_SET_RATE_PARENT, 0x10, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { HI3670_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CLK_SET_RATE_PARENT, 0x10, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { HI3670_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) CLK_SET_RATE_PARENT, 0x10, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { HI3670_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CLK_SET_RATE_PARENT, 0x10, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { HI3670_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CLK_SET_RATE_PARENT, 0x10, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { HI3670_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CLK_SET_RATE_PARENT, 0x10, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { HI3670_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CLK_SET_RATE_PARENT, 0x10, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { HI3670_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CLK_SET_RATE_PARENT, 0x10, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { HI3670_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CLK_SET_RATE_PARENT, 0x10, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { HI3670_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CLK_SET_RATE_PARENT, 0x10, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { HI3670_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) CLK_SET_RATE_PARENT, 0x10, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { HI3670_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CLK_SET_RATE_PARENT, 0x10, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { HI3670_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CLK_SET_RATE_PARENT, 0x10, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { HI3670_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLK_SET_RATE_PARENT, 0x10, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { HI3670_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CLK_SET_RATE_PARENT, 0x10, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { HI3670_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLK_SET_RATE_PARENT, 0x50, 28, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { HI3670_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CLK_SET_RATE_PARENT, 0x50, 29, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { HI3670_HCLK_GATE_USB3OTG, "hclk_gate_usb3otg", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_SET_RATE_PARENT, 0x0, 25, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { HI3670_ACLK_GATE_USB3DVFS, "aclk_gate_usb3dvfs", "autodiv_emmc0bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CLK_SET_RATE_PARENT, 0x40, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { HI3670_HCLK_GATE_SDIO, "hclk_gate_sdio", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CLK_SET_RATE_PARENT, 0x0, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { HI3670_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CLK_SET_RATE_PARENT, 0x420, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { HI3670_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "pclk_gate_mmc1_pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK_SET_RATE_PARENT, 0x420, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { HI3670_PCLK_GATE_MMC1_PCIE, "pclk_gate_mmc1_pcie", "pclk_div_mmc1_pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CLK_SET_RATE_PARENT, 0x30, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { HI3670_PCLK_GATE_MMC0_IOC, "pclk_gate_mmc0_ioc", "clk_div_mmc0bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLK_SET_RATE_PARENT, 0x40, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { HI3670_PCLK_GATE_MMC1_IOC, "pclk_gate_mmc1_ioc", "clk_div_mmc1bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CLK_SET_RATE_PARENT, 0x420, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { HI3670_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CLK_SET_RATE_PARENT, 0x30, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { HI3670_CLK_GATE_VCODECBUS2DDR, "clk_gate_vcodecbus2ddr", "clk_div_vcodecbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CLK_SET_RATE_PARENT, 0x0, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { HI3670_CLK_CCI400_BYPASS, "clk_cci400_bypass", "clk_ddrc_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CLK_SET_RATE_PARENT, 0x22C, 28, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { HI3670_CLK_GATE_CCI400, "clk_gate_cci400", "clk_ddrc_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) CLK_SET_RATE_PARENT, 0x50, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { HI3670_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CLK_SET_RATE_PARENT, 0x40, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { HI3670_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CLK_SET_RATE_PARENT, 0x0, 30, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { HI3670_CLK_GATE_SDIO, "clk_gate_sdio", "clk_mux_sdio_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CLK_SET_RATE_PARENT, 0x40, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { HI3670_CLK_GATE_A57HPM, "clk_gate_a57hpm", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CLK_SET_RATE_PARENT, 0x050, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { HI3670_CLK_GATE_A53HPM, "clk_gate_a53hpm", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CLK_SET_RATE_PARENT, 0x050, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { HI3670_CLK_GATE_PA_A53, "clk_gate_pa_a53", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CLK_SET_RATE_PARENT, 0x480, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { HI3670_CLK_GATE_PA_A57, "clk_gate_pa_a57", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CLK_SET_RATE_PARENT, 0x480, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { HI3670_CLK_GATE_PA_G3D, "clk_gate_pa_g3d", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) CLK_SET_RATE_PARENT, 0x480, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { HI3670_CLK_GATE_GPUHPM, "clk_gate_gpuhpm", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) CLK_SET_RATE_PARENT, 0x050, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { HI3670_CLK_GATE_PERIHPM, "clk_gate_perihpm", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CLK_SET_RATE_PARENT, 0x050, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { HI3670_CLK_GATE_AOHPM, "clk_gate_aohpm", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CLK_SET_RATE_PARENT, 0x050, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { HI3670_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CLK_SET_RATE_PARENT, 0x20, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { HI3670_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CLK_SET_RATE_PARENT, 0x20, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { HI3670_PCLK_GATE_UART1, "pclk_gate_uart1", "clk_mux_uarth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CLK_SET_RATE_PARENT, 0x20, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { HI3670_PCLK_GATE_UART4, "pclk_gate_uart4", "clk_mux_uarth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CLK_SET_RATE_PARENT, 0x20, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { HI3670_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uartl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CLK_SET_RATE_PARENT, 0x20, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { HI3670_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uartl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CLK_SET_RATE_PARENT, 0x20, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { HI3670_PCLK_GATE_UART2, "pclk_gate_uart2", "clk_mux_uartl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) CLK_SET_RATE_PARENT, 0x20, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { HI3670_PCLK_GATE_UART5, "pclk_gate_uart5", "clk_mux_uartl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CLK_SET_RATE_PARENT, 0x20, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { HI3670_CLK_GATE_UART0, "clk_gate_uart0", "clk_mux_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CLK_SET_RATE_PARENT, 0x20, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { HI3670_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CLK_SET_RATE_PARENT, 0x20, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { HI3670_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CLK_SET_RATE_PARENT, 0x20, 27, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { HI3670_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CLK_SET_RATE_PARENT, 0x10, 31, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { HI3670_PCLK_GATE_I2C3, "pclk_gate_i2c3", "clk_mux_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CLK_SET_RATE_PARENT, 0x20, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { HI3670_PCLK_GATE_I2C4, "pclk_gate_i2c4", "clk_mux_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) CLK_SET_RATE_PARENT, 0x20, 27, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { HI3670_PCLK_GATE_I2C7, "pclk_gate_i2c7", "clk_mux_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) CLK_SET_RATE_PARENT, 0x10, 31, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { HI3670_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CLK_SET_RATE_PARENT, 0x20, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { HI3670_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CLK_SET_RATE_PARENT, 0x40, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { HI3670_PCLK_GATE_SPI1, "pclk_gate_spi1", "clk_mux_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CLK_SET_RATE_PARENT, 0x20, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { HI3670_PCLK_GATE_SPI4, "pclk_gate_spi4", "clk_mux_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CLK_SET_RATE_PARENT, 0x40, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { HI3670_CLK_GATE_USB3OTG_REF, "clk_gate_usb3otg_ref", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CLK_SET_RATE_PARENT, 0x40, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { HI3670_CLK_GATE_USB2PHY_REF, "clk_gate_usb2phy_ref", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CLK_SET_RATE_PARENT, 0x410, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { HI3670_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CLK_SET_RATE_PARENT, 0x420, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { HI3670_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_gate_mmc1_pcieaxi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CLK_SET_RATE_PARENT, 0x420, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { HI3670_CLK_GATE_MMC1_PCIEAXI, "clk_gate_mmc1_pcieaxi", "clk_div_pcieaxi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CLK_SET_RATE_PARENT, 0x050, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { HI3670_CLK_GATE_PCIEPHY_REF, "clk_gate_pciephy_ref", "clk_ppll_pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CLK_SET_RATE_PARENT, 0x470, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { HI3670_CLK_GATE_PCIE_DEBOUNCE, "clk_gate_pcie_debounce", "clk_ppll_pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CLK_SET_RATE_PARENT, 0x470, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { HI3670_CLK_GATE_PCIEIO, "clk_gate_pcieio", "clk_ppll_pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) CLK_SET_RATE_PARENT, 0x470, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { HI3670_CLK_GATE_PCIE_HP, "clk_gate_pcie_hp", "clk_ppll_pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CLK_SET_RATE_PARENT, 0x470, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { HI3670_CLK_GATE_AO_ASP, "clk_gate_ao_asp", "clk_div_ao_asp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) CLK_SET_RATE_PARENT, 0x0, 26, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { HI3670_PCLK_GATE_PCTRL, "pclk_gate_pctrl", "clk_div_ptp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) CLK_SET_RATE_PARENT, 0x20, 31, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { HI3670_CLK_CSI_TRANS_GT, "clk_csi_trans_gt", "clk_div_csi_trans",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CLK_SET_RATE_PARENT, 0x30, 24, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { HI3670_CLK_DSI_TRANS_GT, "clk_dsi_trans_gt", "clk_div_dsi_trans",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CLK_SET_RATE_PARENT, 0x30, 25, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { HI3670_CLK_GATE_PWM, "clk_gate_pwm", "clk_div_ptp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CLK_SET_RATE_PARENT, 0x20, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { HI3670_ABB_AUDIO_EN0, "abb_audio_en0", "clk_gate_abb_192",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CLK_SET_RATE_PARENT, 0x30, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { HI3670_ABB_AUDIO_EN1, "abb_audio_en1", "clk_gate_abb_192",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CLK_SET_RATE_PARENT, 0x30, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { HI3670_ABB_AUDIO_GT_EN0, "abb_audio_gt_en0", "abb_audio_en0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) CLK_SET_RATE_PARENT, 0x30, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { HI3670_ABB_AUDIO_GT_EN1, "abb_audio_gt_en1", "abb_audio_en1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) CLK_SET_RATE_PARENT, 0x40, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { HI3670_CLK_GATE_DP_AUDIO_PLL_AO, "clk_gate_dp_audio_pll_ao", "clkdiv_dp_audio_pll_ao",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) CLK_SET_RATE_PARENT, 0x00, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { HI3670_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CLK_SET_RATE_PARENT, 0, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { HI3670_PERI_VOLT_MIDDLE, "peri_volt_middle", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) CLK_SET_RATE_PARENT, 0, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { HI3670_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0", "clk_isp_snclk_mux0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) CLK_SET_RATE_PARENT, 0x50, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { HI3670_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1", "clk_isp_snclk_mux1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) CLK_SET_RATE_PARENT, 0x50, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { HI3670_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2", "clk_isp_snclk_mux2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CLK_SET_RATE_PARENT, 0x50, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { HI3670_CLK_GATE_RXDPHY0_CFG, "clk_gate_rxdphy0_cfg", "clk_mux_rxdphy_cfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) CLK_SET_RATE_PARENT, 0x030, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { HI3670_CLK_GATE_RXDPHY1_CFG, "clk_gate_rxdphy1_cfg", "clk_mux_rxdphy_cfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) CLK_SET_RATE_PARENT, 0x030, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { HI3670_CLK_GATE_RXDPHY2_CFG, "clk_gate_rxdphy2_cfg", "clk_mux_rxdphy_cfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) CLK_SET_RATE_PARENT, 0x030, 22, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { HI3670_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CLK_SET_RATE_PARENT, 0x030, 28, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { HI3670_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CLK_SET_RATE_PARENT, 0x030, 29, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { HI3670_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) CLK_SET_RATE_PARENT, 0x030, 30, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { HI3670_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CLK_SET_RATE_PARENT, 0x030, 31, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { HI3670_CLK_GATE_MEDIA_TCXO, "clk_gate_media_tcxo", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) CLK_SET_RATE_PARENT, 0x40, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct hisi_gate_clock hi3670_crgctrl_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { HI3670_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { HI3670_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { HI3670_PCLK_ANDGT_MMC1_PCIE, "pclk_andgt_mmc1_pcie", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CLK_SET_RATE_PARENT, 0xf8, 13, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { HI3670_CLK_GATE_VCODECBUS_GT, "clk_gate_vcodecbus_gt", "clk_mux_vcodecbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CLK_SET_RATE_PARENT, 0x0F0, 8, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { HI3670_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CLK_SET_RATE_PARENT, 0xF4, 3, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { HI3670_CLK_SD_SYS_GT, "clk_sd_sys_gt", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) CLK_SET_RATE_PARENT, 0xF4, 5, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { HI3670_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) CLK_SET_RATE_PARENT, 0xF4, 8, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { HI3670_CLK_SDIO_SYS_GT, "clk_sdio_sys_gt", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) CLK_SET_RATE_PARENT, 0xF4, 6, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { HI3670_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) CLK_SET_RATE_PARENT, 0x0F4, 7, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { HI3670_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CLK_SET_RATE_PARENT, 0xF8, 10, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { HI3670_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) CLK_SET_RATE_PARENT, 0xF4, 11, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { HI3670_CLK_ANDGT_UARTL, "clk_andgt_uartl", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) CLK_SET_RATE_PARENT, 0xF4, 10, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { HI3670_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) CLK_SET_RATE_PARENT, 0xF4, 9, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { HI3670_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CLK_SET_RATE_PARENT, 0xF4, 13, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { HI3670_CLK_ANDGT_PCIEAXI, "clk_andgt_pcieaxi", "clk_mux_pcieaxi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CLK_SET_RATE_PARENT, 0xfc, 15, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { HI3670_CLK_DIV_AO_ASP_GT, "clk_div_ao_asp_gt", "clk_mux_ao_asp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) CLK_SET_RATE_PARENT, 0xF4, 4, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { HI3670_CLK_GATE_CSI_TRANS, "clk_gate_csi_trans", "clk_ppll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) CLK_SET_RATE_PARENT, 0xF4, 14, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { HI3670_CLK_GATE_DSI_TRANS, "clk_gate_dsi_trans", "clk_ppll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { HI3670_CLK_ANDGT_PTP, "clk_andgt_ptp", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { HI3670_CLK_ANDGT_OUT0, "clk_andgt_out0", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { HI3670_CLK_ANDGT_OUT1, "clk_andgt_out1", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { HI3670_CLKGT_DP_AUDIO_PLL_AO, "clkgt_dp_audio_pll_ao", "clk_ppll6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) CLK_SET_RATE_PARENT, 0xF8, 15, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { HI3670_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CLK_SET_RATE_PARENT, 0xF0, 13, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { HI3670_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CLK_SET_RATE_PARENT, 0xF0, 9, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { HI3670_CLK_ISP_SNCLK_ANGT, "clk_isp_snclk_angt", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { HI3670_CLK_ANDGT_RXDPHY, "clk_andgt_rxdphy", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CLK_SET_RATE_PARENT, 0x0F0, 12, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { HI3670_CLK_ANDGT_ICS, "clk_andgt_ics", "clk_mux_ics",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CLK_SET_RATE_PARENT, 0xf0, 14, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { HI3670_AUTODIV_DMABUS, "autodiv_dmabus", "autodiv_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) CLK_SET_RATE_PARENT, 0x404, 3, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) clk_mux_sysbus_p[] = { "clk_ppll1", "clk_ppll0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clk_mux_vcodecbus_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "clk_invalid", "clk_ppll2", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "clk_invalid", "clk_invalid", "clk_ppll3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "clk_invalid", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) clk_mux_sd_sys_p[] = { "clk_sd_sys", "clk_div_sd", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) clk_mux_sd_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) clk_mux_sdio_sys_p[] = { "clk_sdio_sys", "clk_div_sdio", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) clk_mux_sdio_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) clk_mux_a53hpm_p[] = { "clk_ppll0", "clk_ppll2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) clk_mux_320m_p[] = { "clk_ppll2", "clk_ppll0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) clk_mux_uarth_p[] = { "clkin_sys", "clk_div_uarth", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) clk_mux_uartl_p[] = { "clkin_sys", "clk_div_uartl", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) clk_mux_uart0_p[] = { "clkin_sys", "clk_div_uart0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) clk_mux_i2c_p[] = { "clkin_sys", "clk_div_i2c", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) clk_mux_spi_p[] = { "clkin_sys", "clk_div_spi", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clk_mux_pcieaxi_p[] = { "clkin_sys", "clk_ppll0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) clk_mux_ao_asp_p[] = { "clk_ppll2", "clk_ppll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk_mux_vdec_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "clk_invalid", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) clk_mux_venc_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "clk_invalid", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk_isp_snclk_mux0_p[] = { "clkin_sys", "clk_isp_snclk_div0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) clk_isp_snclk_mux1_p[] = { "clkin_sys", "clk_isp_snclk_div1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) clk_isp_snclk_mux2_p[] = { "clkin_sys", "clk_isp_snclk_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) clk_mux_rxdphy_cfg_p[] = { "clk_factor_rxdphy", "clkin_sys", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clk_mux_ics_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "clk_ppll2", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "clk_ppll3", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "clk_invalid", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct hisi_mux_clock hi3670_crgctrl_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { HI3670_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0xAC, 0, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { HI3670_CLK_MUX_VCODECBUS, "clk_mux_vcodecbus", clk_mux_vcodecbus_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ARRAY_SIZE(clk_mux_vcodecbus_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { HI3670_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { HI3670_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_sd_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ARRAY_SIZE(clk_mux_sd_pll_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { HI3670_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { HI3670_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_sdio_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ARRAY_SIZE(clk_mux_sdio_pll_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { HI3670_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_a53hpm_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ARRAY_SIZE(clk_mux_a53hpm_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { HI3670_CLK_MUX_320M, "clk_mux_320m", clk_mux_320m_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ARRAY_SIZE(clk_mux_320m_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 0x100, 0, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { HI3670_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 0xAC, 4, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { HI3670_CLK_MUX_UARTL, "clk_mux_uartl", clk_mux_uartl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ARRAY_SIZE(clk_mux_uartl_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0xAC, 3, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { HI3670_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 0xAC, 2, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { HI3670_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0xAC, 13, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { HI3670_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0xAC, 8, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { HI3670_CLK_MUX_PCIEAXI, "clk_mux_pcieaxi", clk_mux_pcieaxi_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ARRAY_SIZE(clk_mux_pcieaxi_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0xb4, 5, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { HI3670_CLK_MUX_AO_ASP, "clk_mux_ao_asp", clk_mux_ao_asp_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ARRAY_SIZE(clk_mux_ao_asp_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 0x100, 6, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { HI3670_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_vdec_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ARRAY_SIZE(clk_mux_vdec_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0xC8, 8, 4, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { HI3670_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0xC8, 4, 4, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { HI3670_CLK_ISP_SNCLK_MUX0, "clk_isp_snclk_mux0", clk_isp_snclk_mux0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ARRAY_SIZE(clk_isp_snclk_mux0_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0x108, 3, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { HI3670_CLK_ISP_SNCLK_MUX1, "clk_isp_snclk_mux1", clk_isp_snclk_mux1_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ARRAY_SIZE(clk_isp_snclk_mux1_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 0x10C, 13, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { HI3670_CLK_ISP_SNCLK_MUX2, "clk_isp_snclk_mux2", clk_isp_snclk_mux2_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ARRAY_SIZE(clk_isp_snclk_mux2_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 0x10C, 10, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { HI3670_CLK_MUX_RXDPHY_CFG, "clk_mux_rxdphy_cfg", clk_mux_rxdphy_cfg_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ARRAY_SIZE(clk_mux_rxdphy_cfg_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 0x0C4, 8, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { HI3670_CLK_MUX_ICS, "clk_mux_ics", clk_mux_ics_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ARRAY_SIZE(clk_mux_ics_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 0xc8, 12, 4, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const struct hisi_divider_clock hi3670_crgctrl_divider_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { HI3670_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { HI3670_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { HI3670_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { HI3670_PCLK_DIV_MMC1_PCIE, "pclk_div_mmc1_pcie", "pclk_andgt_mmc1_pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { HI3670_CLK_DIV_VCODECBUS, "clk_div_vcodecbus", "clk_gate_vcodecbus_gt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { HI3670_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { HI3670_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { HI3670_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { HI3670_CLK_DIV_UARTL, "clk_div_uartl", "clk_andgt_uartl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { HI3670_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { HI3670_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) CLK_SET_RATE_PARENT, 0xE8, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { HI3670_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) CLK_SET_RATE_PARENT, 0xC4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { HI3670_CLK_DIV_PCIEAXI, "clk_div_pcieaxi", "clk_andgt_pcieaxi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) CLK_SET_RATE_PARENT, 0xb4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { HI3670_CLK_DIV_AO_ASP, "clk_div_ao_asp", "clk_div_ao_asp_gt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) CLK_SET_RATE_PARENT, 0x108, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) { HI3670_CLK_DIV_CSI_TRANS, "clk_div_csi_trans", "clk_gate_csi_trans",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) CLK_SET_RATE_PARENT, 0xD4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { HI3670_CLK_DIV_DSI_TRANS, "clk_div_dsi_trans", "clk_gate_dsi_trans",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) CLK_SET_RATE_PARENT, 0xD4, 10, 5, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { HI3670_CLK_DIV_PTP, "clk_div_ptp", "clk_andgt_ptp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) CLK_SET_RATE_PARENT, 0xD8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { HI3670_CLK_DIV_CLKOUT0_PLL, "clk_div_clkout0_pll", "clk_andgt_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) CLK_SET_RATE_PARENT, 0xe0, 4, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { HI3670_CLK_DIV_CLKOUT1_PLL, "clk_div_clkout1_pll", "clk_andgt_out1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CLK_SET_RATE_PARENT, 0xe0, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { HI3670_CLKDIV_DP_AUDIO_PLL_AO, "clkdiv_dp_audio_pll_ao", "clkgt_dp_audio_pll_ao",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) CLK_SET_RATE_PARENT, 0xBC, 11, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { HI3670_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) CLK_SET_RATE_PARENT, 0xC4, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { HI3670_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) CLK_SET_RATE_PARENT, 0xC0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { HI3670_CLK_ISP_SNCLK_DIV0, "clk_isp_snclk_div0", "clk_isp_snclk_fac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { HI3670_CLK_ISP_SNCLK_DIV1, "clk_isp_snclk_div1", "clk_isp_snclk_fac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) CLK_SET_RATE_PARENT, 0x10C, 14, 2, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { HI3670_CLK_ISP_SNCLK_DIV2, "clk_isp_snclk_div2", "clk_isp_snclk_fac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) CLK_SET_RATE_PARENT, 0x10C, 11, 2, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { HI3670_CLK_DIV_ICS, "clk_div_ics", "clk_andgt_ics",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) CLK_SET_RATE_PARENT, 0xE4, 9, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* clk_pmuctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct hisi_gate_clock hi3670_pmu_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { HI3670_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) CLK_SET_RATE_PARENT, (0x037 << 2), 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* clk_pctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct hisi_gate_clock hi3670_pctrl_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { HI3670_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en", "clk_gate_abb_192",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) CLK_SET_RATE_PARENT, 0x10, 0, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { HI3670_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* clk_sctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct hisi_gate_clock hi3670_sctrl_gate_sep_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { HI3670_PPLL0_EN_ACPU, "ppll0_en_acpu", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) CLK_SET_RATE_PARENT, 0x190, 26, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { HI3670_PPLL0_GT_CPU, "ppll0_gt_cpu", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) CLK_SET_RATE_PARENT, 0x190, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { HI3670_CLK_GATE_PPLL0_MEDIA, "clk_gate_ppll0_media", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) CLK_SET_RATE_PARENT, 0x1b0, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { HI3670_PCLK_GPIO18, "pclk_gpio18", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) CLK_SET_RATE_PARENT, 0x1B0, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { HI3670_PCLK_GPIO19, "pclk_gpio19", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) CLK_SET_RATE_PARENT, 0x1B0, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { HI3670_CLK_GATE_SPI, "clk_gate_spi", "clk_div_ioperi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { HI3670_PCLK_GATE_SPI, "pclk_gate_spi", "clk_div_ioperi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { HI3670_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_ufs_subsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) CLK_SET_RATE_PARENT, 0x1B0, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { HI3670_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) CLK_SET_RATE_PARENT, 0x1b0, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { HI3670_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) CLK_SET_RATE_PARENT, 0x160, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { HI3670_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) CLK_SET_RATE_PARENT, 0x160, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) { HI3670_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CLK_SET_RATE_PARENT, 0x160, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { HI3670_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) CLK_SET_RATE_PARENT, 0x160, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { HI3670_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) CLK_SET_RATE_PARENT, 0x160, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { HI3670_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) CLK_SET_RATE_PARENT, 0x160, 22, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { HI3670_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) CLK_SET_RATE_PARENT, 0x160, 25, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { HI3670_CLK_GATE_OUT0, "clk_gate_out0", "clk_mux_clkout0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) CLK_SET_RATE_PARENT, 0x160, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { HI3670_CLK_GATE_OUT1, "clk_gate_out1", "clk_mux_clkout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) CLK_SET_RATE_PARENT, 0x160, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { HI3670_PCLK_GATE_SYSCNT, "pclk_gate_syscnt", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) CLK_SET_RATE_PARENT, 0x160, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { HI3670_CLK_GATE_SYSCNT, "clk_gate_syscnt", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) CLK_SET_RATE_PARENT, 0x160, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { HI3670_CLK_GATE_ASP_SUBSYS_PERI, "clk_gate_asp_subsys_peri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "clk_mux_asp_subsys_peri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) CLK_SET_RATE_PARENT, 0x170, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { HI3670_CLK_GATE_ASP_SUBSYS, "clk_gate_asp_subsys", "clk_mux_asp_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) CLK_SET_RATE_PARENT, 0x170, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { HI3670_CLK_GATE_ASP_TCXO, "clk_gate_asp_tcxo", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) CLK_SET_RATE_PARENT, 0x160, 27, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { HI3670_CLK_GATE_DP_AUDIO_PLL, "clk_gate_dp_audio_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) "clk_gate_dp_audio_pll_ao",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) CLK_SET_RATE_PARENT, 0x1B0, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const struct hisi_gate_clock hi3670_sctrl_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { HI3670_CLK_ANDGT_IOPERI, "clk_andgt_ioperi", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) CLK_SET_RATE_PARENT, 0x270, 6, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { HI3670_CLKANDGT_ASP_SUBSYS_PERI, "clkandgt_asp_subsys_peri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) CLK_SET_RATE_PARENT, 0x268, 3, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { HI3670_CLK_ANGT_ASP_SUBSYS, "clk_angt_asp_subsys", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) CLK_SET_RATE_PARENT, 0x258, 0, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) clk_mux_ufs_subsys_p[] = { "clkin_sys", "clk_ppll0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) clk_mux_clkout0_p[] = { "clkin_ref", "clk_div_clkout0_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "clk_div_clkout0_pll", "clk_div_clkout0_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) clk_mux_clkout1_p[] = { "clkin_ref", "clk_div_clkout1_tcxo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "clk_div_clkout1_pll", "clk_div_clkout1_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) clk_mux_asp_subsys_peri_p[] = { "clk_ppll0", "clk_fll_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) clk_mux_asp_pll_p[] = { "clk_ppll0", "clk_fll_src", "clk_gate_ao_asp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "clk_pciepll_rev", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const struct hisi_mux_clock hi3670_sctrl_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { HI3670_CLK_MUX_UFS_SUBSYS, "clk_mux_ufs_subsys", clk_mux_ufs_subsys_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ARRAY_SIZE(clk_mux_ufs_subsys_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0x274, 8, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { HI3670_CLK_MUX_CLKOUT0, "clk_mux_clkout0", clk_mux_clkout0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ARRAY_SIZE(clk_mux_clkout0_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 0x254, 12, 2, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { HI3670_CLK_MUX_CLKOUT1, "clk_mux_clkout1", clk_mux_clkout1_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ARRAY_SIZE(clk_mux_clkout1_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 0x254, 14, 2, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { HI3670_CLK_MUX_ASP_SUBSYS_PERI, "clk_mux_asp_subsys_peri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) clk_mux_asp_subsys_peri_p, ARRAY_SIZE(clk_mux_asp_subsys_peri_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) CLK_SET_RATE_PARENT, 0x268, 8, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { HI3670_CLK_MUX_ASP_PLL, "clk_mux_asp_pll", clk_mux_asp_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ARRAY_SIZE(clk_mux_asp_pll_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 0x268, 9, 2, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const struct hisi_divider_clock hi3670_sctrl_divider_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { HI3670_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { HI3670_CLK_DIV_UFS_SUBSYS, "clk_div_ufs_subsys", "clk_mux_ufs_subsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) CLK_SET_RATE_PARENT, 0x274, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { HI3670_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_andgt_ioperi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) CLK_SET_RATE_PARENT, 0x270, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { HI3670_CLK_DIV_CLKOUT0_TCXO, "clk_div_clkout0_tcxo", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) CLK_SET_RATE_PARENT, 0x254, 6, 3, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { HI3670_CLK_DIV_CLKOUT1_TCXO, "clk_div_clkout1_tcxo", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) CLK_SET_RATE_PARENT, 0x254, 9, 3, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { HI3670_CLK_ASP_SUBSYS_PERI_DIV, "clk_asp_subsys_peri_div", "clkandgt_asp_subsys_peri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) CLK_SET_RATE_PARENT, 0x268, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { HI3670_CLK_DIV_ASP_SUBSYS, "clk_div_asp_subsys", "clk_angt_asp_subsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) CLK_SET_RATE_PARENT, 0x250, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* clk_iomcu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const struct hisi_fixed_factor_clock hi3670_iomcu_fixed_factor_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { HI3670_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_gate_iomcu", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { HI3670_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_gate_iomcu", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { HI3670_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_gate_iomcu", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { HI3670_CLK_GATE_SPI0, "clk_gate_spi0", "clk_spi0_gate_iomcu", 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { HI3670_CLK_GATE_SPI2, "clk_gate_spi2", "clk_spi2_gate_iomcu", 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { HI3670_CLK_GATE_UART3, "clk_gate_uart3", "clk_uart3_gate_iomcu", 1, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const struct hisi_gate_clock hi3670_iomcu_gate_sep_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { HI3670_CLK_I2C0_GATE_IOMCU, "clk_i2c0_gate_iomcu", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) CLK_SET_RATE_PARENT, 0x10, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { HI3670_CLK_I2C1_GATE_IOMCU, "clk_i2c1_gate_iomcu", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) CLK_SET_RATE_PARENT, 0x10, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { HI3670_CLK_I2C2_GATE_IOMCU, "clk_i2c2_gate_iomcu", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) CLK_SET_RATE_PARENT, 0x10, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) { HI3670_CLK_SPI0_GATE_IOMCU, "clk_spi0_gate_iomcu", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) CLK_SET_RATE_PARENT, 0x10, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) { HI3670_CLK_SPI2_GATE_IOMCU, "clk_spi2_gate_iomcu", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) CLK_SET_RATE_PARENT, 0x10, 30, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) { HI3670_CLK_UART3_GATE_IOMCU, "clk_uart3_gate_iomcu", "clk_gate_iomcu_peri0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) CLK_SET_RATE_PARENT, 0x10, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) { HI3670_CLK_GATE_PERI0_IOMCU, "clk_gate_iomcu_peri0", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) CLK_SET_RATE_PARENT, 0x90, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* clk_media1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const struct hisi_gate_clock hi3670_media1_gate_sep_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { HI3670_ACLK_GATE_NOC_DSS, "aclk_gate_noc_dss", "aclk_gate_disp_noc_subsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) CLK_SET_RATE_PARENT, 0x10, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { HI3670_PCLK_GATE_NOC_DSS_CFG, "pclk_gate_noc_dss_cfg", "pclk_gate_disp_noc_subsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) CLK_SET_RATE_PARENT, 0x10, 22, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { HI3670_PCLK_GATE_MMBUF_CFG, "pclk_gate_mmbuf_cfg", "pclk_gate_disp_noc_subsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) CLK_SET_RATE_PARENT, 0x20, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { HI3670_PCLK_GATE_DISP_NOC_SUBSYS, "pclk_gate_disp_noc_subsys", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) CLK_SET_RATE_PARENT, 0x10, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { HI3670_ACLK_GATE_DISP_NOC_SUBSYS, "aclk_gate_disp_noc_subsys", "clk_gate_vivobusfreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) CLK_SET_RATE_PARENT, 0x10, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { HI3670_PCLK_GATE_DSS, "pclk_gate_dss", "pclk_gate_disp_noc_subsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) CLK_SET_RATE_PARENT, 0x00, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { HI3670_ACLK_GATE_DSS, "aclk_gate_dss", "aclk_gate_disp_noc_subsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) CLK_SET_RATE_PARENT, 0x00, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { HI3670_CLK_GATE_VIVOBUSFREQ, "clk_gate_vivobusfreq", "clk_div_vivobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) CLK_SET_RATE_PARENT, 0x00, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { HI3670_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) CLK_SET_RATE_PARENT, 0x00, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { HI3670_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) CLK_SET_RATE_PARENT, 0x00, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { HI3670_CLK_GATE_LDI1FREQ, "clk_gate_ldi1freq", "clk_div_ldi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) CLK_SET_RATE_PARENT, 0x00, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { HI3670_CLK_GATE_BRG, "clk_gate_brg", "clk_media_common_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) CLK_SET_RATE_PARENT, 0x00, 29, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { HI3670_ACLK_GATE_ASC, "aclk_gate_asc", "clk_gate_mmbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) CLK_SET_RATE_PARENT, 0x20, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) { HI3670_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "clk_gate_mmbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) CLK_SET_RATE_PARENT, 0x20, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) { HI3670_CLK_GATE_MMBUF, "clk_gate_mmbuf", "aclk_div_mmbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) CLK_SET_RATE_PARENT, 0x20, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { HI3670_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) CLK_SET_RATE_PARENT, 0x20, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) { HI3670_CLK_GATE_ATDIV_VIVO, "clk_gate_atdiv_vivo", "clk_div_vivobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) CLK_SET_RATE_PARENT, 0x010, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const struct hisi_gate_clock hi3670_media1_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) { HI3670_CLK_GATE_VIVOBUS_ANDGT, "clk_gate_vivobus_andgt", "clk_mux_vivobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) CLK_SET_RATE_PARENT, 0x84, 3, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { HI3670_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) CLK_SET_RATE_PARENT, 0x84, 7, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { HI3670_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) CLK_SET_RATE_PARENT, 0x84, 9, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) { HI3670_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) CLK_SET_RATE_PARENT, 0x84, 8, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) { HI3670_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_sw_mmbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) CLK_SET_RATE_PARENT, 0x84, 14, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) { HI3670_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "aclk_div_mmbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) CLK_SET_RATE_PARENT, 0x84, 15, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) clk_mux_vivobus_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "clk_invalid", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) clk_mux_edc0_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "clk_invalid", "clk_invalid", "clk_invalid", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) clk_mux_ldi0_p[] = { "clk_invalid", "clk_gate_ppll7_media",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "clk_gate_ppll0_media", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "clk_gate_ppll2_media", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "clk_invalid", "clk_gate_ppll3_media", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "clk_invalid", "clk_invalid", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) clk_mux_ldi1_p[] = { "clk_invalid", "clk_gate_ppll7_media",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "clk_gate_ppll0_media", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "clk_gate_ppll2_media", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "clk_invalid", "clk_gate_ppll3_media", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "clk_invalid", "clk_invalid", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) clk_sw_mmbuf_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) "clk_invalid", "clk_invalid", "clk_invalid", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static const struct hisi_mux_clock hi3670_media1_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) { HI3670_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_vivobus_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ARRAY_SIZE(clk_mux_vivobus_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 0x74, 6, 4, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) { HI3670_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 0x68, 6, 4, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) { HI3670_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 0x60, 6, 4, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) { HI3670_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi1_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ARRAY_SIZE(clk_mux_ldi1_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 0x64, 6, 4, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) { HI3670_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 0x88, 0, 4, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const struct hisi_divider_clock hi3670_media1_divider_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) { HI3670_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_gate_vivobus_andgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) CLK_SET_RATE_PARENT, 0x74, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) { HI3670_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) CLK_SET_RATE_PARENT, 0x68, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { HI3670_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) CLK_SET_RATE_PARENT, 0x60, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { HI3670_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) CLK_SET_RATE_PARENT, 0x64, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) { HI3670_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) CLK_SET_RATE_PARENT, 0x7C, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) { HI3670_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) CLK_SET_RATE_PARENT, 0x78, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* clk_media2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const struct hisi_gate_clock hi3670_media2_gate_sep_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { HI3670_CLK_GATE_VDECFREQ, "clk_gate_vdecfreq", "clk_div_vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) CLK_SET_RATE_PARENT, 0x00, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { HI3670_CLK_GATE_VENCFREQ, "clk_gate_vencfreq", "clk_div_venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) CLK_SET_RATE_PARENT, 0x00, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { HI3670_CLK_GATE_ICSFREQ, "clk_gate_icsfreq", "clk_div_ics",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) CLK_SET_RATE_PARENT, 0x00, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static void hi3670_clk_crgctrl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int nr = ARRAY_SIZE(hi3670_fixed_rate_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ARRAY_SIZE(hi3670_crgctrl_gate_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ARRAY_SIZE(hi3670_crgctrl_mux_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ARRAY_SIZE(hi3670_crg_fixed_factor_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ARRAY_SIZE(hi3670_crgctrl_divider_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) hisi_clk_register_fixed_rate(hi3670_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ARRAY_SIZE(hi3670_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) hisi_clk_register_gate_sep(hi3670_crgctrl_gate_sep_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) hisi_clk_register_gate(hi3670_crgctrl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ARRAY_SIZE(hi3670_crgctrl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) hisi_clk_register_mux(hi3670_crgctrl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ARRAY_SIZE(hi3670_crgctrl_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) hisi_clk_register_fixed_factor(hi3670_crg_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ARRAY_SIZE(hi3670_crg_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) hisi_clk_register_divider(hi3670_crgctrl_divider_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ARRAY_SIZE(hi3670_crgctrl_divider_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static void hi3670_clk_pctrl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int nr = ARRAY_SIZE(hi3670_pctrl_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) hisi_clk_register_gate(hi3670_pctrl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static void hi3670_clk_pmuctrl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int nr = ARRAY_SIZE(hi3670_pmu_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) hisi_clk_register_gate(hi3670_pmu_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static void hi3670_clk_sctrl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int nr = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ARRAY_SIZE(hi3670_sctrl_gate_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ARRAY_SIZE(hi3670_sctrl_mux_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ARRAY_SIZE(hi3670_sctrl_divider_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) hisi_clk_register_gate_sep(hi3670_sctrl_gate_sep_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ARRAY_SIZE(hi3670_sctrl_gate_sep_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) hisi_clk_register_gate(hi3670_sctrl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ARRAY_SIZE(hi3670_sctrl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) hisi_clk_register_mux(hi3670_sctrl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ARRAY_SIZE(hi3670_sctrl_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) hisi_clk_register_divider(hi3670_sctrl_divider_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ARRAY_SIZE(hi3670_sctrl_divider_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static void hi3670_clk_iomcu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int nr = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) hisi_clk_register_gate(hi3670_iomcu_gate_sep_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) hisi_clk_register_fixed_factor(hi3670_iomcu_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static void hi3670_clk_media1_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int nr = ARRAY_SIZE(hi3670_media1_gate_sep_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ARRAY_SIZE(hi3670_media1_gate_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ARRAY_SIZE(hi3670_media1_mux_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ARRAY_SIZE(hi3670_media1_divider_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) hisi_clk_register_gate_sep(hi3670_media1_gate_sep_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ARRAY_SIZE(hi3670_media1_gate_sep_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) hisi_clk_register_gate(hi3670_media1_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ARRAY_SIZE(hi3670_media1_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) hisi_clk_register_mux(hi3670_media1_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ARRAY_SIZE(hi3670_media1_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) hisi_clk_register_divider(hi3670_media1_divider_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ARRAY_SIZE(hi3670_media1_divider_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static void hi3670_clk_media2_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) hisi_clk_register_gate_sep(hi3670_media2_gate_sep_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ARRAY_SIZE(hi3670_media2_gate_sep_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static const struct of_device_id hi3670_clk_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { .compatible = "hisilicon,hi3670-crgctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .data = hi3670_clk_crgctrl_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { .compatible = "hisilicon,hi3670-pctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .data = hi3670_clk_pctrl_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) { .compatible = "hisilicon,hi3670-pmuctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .data = hi3670_clk_pmuctrl_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) { .compatible = "hisilicon,hi3670-sctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .data = hi3670_clk_sctrl_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) { .compatible = "hisilicon,hi3670-iomcu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .data = hi3670_clk_iomcu_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) { .compatible = "hisilicon,hi3670-media1-crg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .data = hi3670_clk_media1_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) { .compatible = "hisilicon,hi3670-media2-crg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .data = hi3670_clk_media2_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int hi3670_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) void (*init_func)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) init_func = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (!init_func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) init_func(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static struct platform_driver hi3670_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .probe = hi3670_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .name = "hi3670-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .of_match_table = hi3670_clk_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int __init hi3670_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return platform_driver_register(&hi3670_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) core_initcall(hi3670_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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