^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <dt-bindings/clock/hi3660-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) { HI3660_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) { HI3660_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000UL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { HI3660_PCLK, "pclk", NULL, 0, 20000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { HI3660_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { HI3660_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { HI3660_OSC32K, "osc32k", NULL, 0, 32764, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { HI3660_OSC19M, "osc19m", NULL, 0, 19200000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { HI3660_CLK_480M, "clk_480m", NULL, 0, 480000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { HI3660_CLK_INV, "clk_inv", NULL, 0, 10000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* crgctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { HI3660_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_iomcu", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { HI3660_CLK_ABB_USB, "clk_abb_usb", "clk_gate_usb_tcxo_en", 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { HI3660_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold", 1, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { HI3660_CLK_FAC_ISP_SNCLK, "clk_isp_snclk_fac", "clk_isp_snclk_angt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 1, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { HI3660_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CLK_SET_RATE_PARENT, 0x0, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { HI3660_HCLK_GATE_SDIO0, "hclk_gate_sdio0", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CLK_SET_RATE_PARENT, 0x0, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { HI3660_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CLK_SET_RATE_PARENT, 0x0, 30, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { HI3660_CLK_GATE_AOMM, "clk_gate_aomm", "clk_div_aomm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CLK_SET_RATE_PARENT, 0x0, 31, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { HI3660_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) CLK_SET_RATE_PARENT, 0x10, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { HI3660_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CLK_SET_RATE_PARENT, 0x10, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { HI3660_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CLK_SET_RATE_PARENT, 0x10, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { HI3660_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CLK_SET_RATE_PARENT, 0x10, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { HI3660_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CLK_SET_RATE_PARENT, 0x10, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { HI3660_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CLK_SET_RATE_PARENT, 0x10, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { HI3660_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_SET_RATE_PARENT, 0x10, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { HI3660_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) CLK_SET_RATE_PARENT, 0x10, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { HI3660_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) CLK_SET_RATE_PARENT, 0x10, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { HI3660_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) CLK_SET_RATE_PARENT, 0x10, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { HI3660_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CLK_SET_RATE_PARENT, 0x10, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { HI3660_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CLK_SET_RATE_PARENT, 0x10, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { HI3660_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CLK_SET_RATE_PARENT, 0x10, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { HI3660_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CLK_SET_RATE_PARENT, 0x10, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { HI3660_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CLK_SET_RATE_PARENT, 0x10, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { HI3660_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CLK_SET_RATE_PARENT, 0x10, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { HI3660_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CLK_SET_RATE_PARENT, 0x10, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { HI3660_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CLK_SET_RATE_PARENT, 0x10, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { HI3660_PCLK_GPIO18, "pclk_gpio18", "clk_div_ioperi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CLK_SET_RATE_PARENT, 0x10, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { HI3660_PCLK_GPIO19, "pclk_gpio19", "clk_div_ioperi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) CLK_SET_RATE_PARENT, 0x10, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { HI3660_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) CLK_SET_RATE_PARENT, 0x10, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { HI3660_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CLK_SET_RATE_PARENT, 0x10, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { HI3660_CLK_GATE_SPI3, "clk_gate_spi3", "clk_div_ioperi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CLK_SET_RATE_PARENT, 0x10, 30, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { HI3660_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CLK_SET_RATE_PARENT, 0x10, 31, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { HI3660_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CLK_SET_RATE_PARENT, 0x20, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { HI3660_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CLK_SET_RATE_PARENT, 0x20, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { HI3660_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CLK_SET_RATE_PARENT, 0x20, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { HI3660_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CLK_SET_RATE_PARENT, 0x20, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { HI3660_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) CLK_SET_RATE_PARENT, 0x20, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { HI3660_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CLK_SET_RATE_PARENT, 0x20, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { HI3660_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CLK_SET_RATE_PARENT, 0x20, 27, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { HI3660_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CLK_SET_RATE_PARENT, 0x30, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { HI3660_CLK_GATE_VENC, "clk_gate_venc", "clk_div_venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CLK_SET_RATE_PARENT, 0x30, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { HI3660_CLK_GATE_VDEC, "clk_gate_vdec", "clk_div_vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CLK_SET_RATE_PARENT, 0x30, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { HI3660_PCLK_GATE_DSS, "pclk_gate_dss", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CLK_SET_RATE_PARENT, 0x30, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { HI3660_ACLK_GATE_DSS, "aclk_gate_dss", "clk_gate_vivobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CLK_SET_RATE_PARENT, 0x30, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { HI3660_CLK_GATE_LDI1, "clk_gate_ldi1", "clk_div_ldi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) CLK_SET_RATE_PARENT, 0x30, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { HI3660_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CLK_SET_RATE_PARENT, 0x30, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { HI3660_CLK_GATE_VIVOBUS, "clk_gate_vivobus", "clk_div_vivobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CLK_SET_RATE_PARENT, 0x30, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { HI3660_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLK_SET_RATE_PARENT, 0x30, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { HI3660_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CLK_SET_RATE_PARENT, 0x30, 28, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { HI3660_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLK_SET_RATE_PARENT, 0x30, 29, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { HI3660_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CLK_SET_RATE_PARENT, 0x30, 30, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { HI3660_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_SET_RATE_PARENT, 0x30, 31, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { HI3660_ACLK_GATE_USB3OTG, "aclk_gate_usb3otg", "clk_div_mmc0bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CLK_SET_RATE_PARENT, 0x40, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { HI3660_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CLK_SET_RATE_PARENT, 0x40, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { HI3660_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CLK_SET_RATE_PARENT, 0x40, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { HI3660_CLK_GATE_SDIO0, "clk_gate_sdio0", "clk_mux_sdio_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK_SET_RATE_PARENT, 0x40, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { HI3660_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { HI3660_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * clk_gate_ufs_subsys is a system bus clock, mark it as critical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * clock and keep it on for system suspend and resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) CLK_SET_RATE_PARENT, 0x50, 28, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CLK_SET_RATE_PARENT, 0x50, 29, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { HI3660_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_div_mmc1bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CLK_SET_RATE_PARENT, 0x420, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { HI3660_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CLK_SET_RATE_PARENT, 0x420, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { HI3660_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CLK_SET_RATE_PARENT, 0x420, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { HI3660_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "clk_div_mmc1bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CLK_SET_RATE_PARENT, 0x420, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { HI3660_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) CLK_SET_RATE_PARENT, 0xf0, 6, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { HI3660_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CLK_SET_RATE_PARENT, 0xf0, 7, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { HI3660_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) CLK_SET_RATE_PARENT, 0xf0, 8, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { HI3660_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) CLK_SET_RATE_PARENT, 0xf0, 15, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { HI3660_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) CLK_SET_RATE_PARENT, 0xf4, 0, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { HI3660_CLK_GATE_UFSPHY_GT, "clk_gate_ufsphy_gt", "clk_div_ufsperi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CLK_SET_RATE_PARENT, 0xf4, 1, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { HI3660_CLK_ANDGT_MMC, "clk_andgt_mmc", "clk_mux_mmc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CLK_SET_RATE_PARENT, 0xf4, 2, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { HI3660_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CLK_SET_RATE_PARENT, 0xf4, 3, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { HI3660_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CLK_SET_RATE_PARENT, 0xf4, 7, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { HI3660_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CLK_SET_RATE_PARENT, 0xf4, 8, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { HI3660_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CLK_SET_RATE_PARENT, 0xf4, 9, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { HI3660_CLK_ANDGT_UART1, "clk_andgt_uart1", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CLK_SET_RATE_PARENT, 0xf4, 10, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { HI3660_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CLK_SET_RATE_PARENT, 0xf4, 11, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { HI3660_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CLK_SET_RATE_PARENT, 0xf4, 13, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { HI3660_CLK_VIVOBUS_ANDGT, "clk_vivobus_andgt", "clk_mux_vivobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) CLK_SET_RATE_PARENT, 0xf8, 1, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { HI3660_CLK_AOMM_ANDGT, "clk_aomm_andgt", "clk_ppll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CLK_SET_RATE_PARENT, 0xf8, 3, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { HI3660_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CLK_SET_RATE_PARENT, 0xf8, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { HI3660_CLK_ANGT_ISP_SNCLK, "clk_isp_snclk_angt", "clk_div_a53hpm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { HI3660_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { HI3660_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { HI3660_CLK_GATE_UFSPHY_CFG, "clk_gate_ufsphy_cfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "clk_div_ufsphy_cfg", CLK_SET_RATE_PARENT, 0x420, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { HI3660_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "clk_gate_ufs_tcxo_en", CLK_SET_RATE_PARENT, 0x420, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) clk_mux_sysbus_p[] = {"clk_ppll1", "clk_ppll0"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) clk_mux_sd_sys_p[] = {"clk_factor_mmc", "clk_div_sd",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_mux_pll_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll2",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clk_mux_pll0123_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll3",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clk_mux_edc0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll1", "clk_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "clk_ppll2", "clk_inv", "clk_inv", "clk_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) clk_mux_ldi0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll2", "clk_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "clk_ppll1", "clk_inv", "clk_inv", "clk_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) clk_mux_uart0_p[] = {"clkin_sys", "clk_div_uart0",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk_mux_uart1_p[] = {"clkin_sys", "clk_div_uart1",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clk_mux_uarth_p[] = {"clkin_sys", "clk_div_uarth",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clk_mux_pll02p[] = {"clk_ppll0", "clk_ppll2",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) clk_mux_ioperi_p[] = {"clk_div_320m", "clk_div_a53hpm",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk_mux_spi_p[] = {"clkin_sys", "clk_div_spi",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) clk_mux_venc_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll3", "clk_ppll3",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clk_mux_isp_snclk_p[] = {"clkin_sys", "clk_isp_snclk_div"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { HI3660_CLK_MUX_UART1, "clk_mux_uart1", clk_mux_uart1_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ARRAY_SIZE(clk_mux_uart1_p), CLK_SET_RATE_PARENT, 0xac, 3, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { HI3660_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT, 0xac, 4, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { HI3660_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT, 0xac, 8, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { HI3660_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT, 0xac, 13, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { HI3660_CLK_MUX_MMC_PLL, "clk_mux_mmc_pll", clk_mux_pll02p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xb4, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { HI3660_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 8, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { HI3660_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 12, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { HI3660_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xb8, 4, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { HI3660_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT, 0xb8, 6, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { HI3660_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, 0xbc, 6, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { HI3660_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xc0, 6, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { HI3660_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { HI3660_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, 0xc8, 11, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { HI3660_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_pll0123_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xcc, 5, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { HI3660_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_pll0123_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { HI3660_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_pll02p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xd4, 9, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { HI3660_CLK_MUX_320M, "clk_mux_320m", clk_mux_pll02p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0x100, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { HI3660_CLK_MUX_ISP_SNCLK, "clk_isp_snclk_mux", clk_mux_isp_snclk_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ARRAY_SIZE(clk_mux_isp_snclk_p), CLK_SET_RATE_PARENT, 0x108, 3, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { HI3660_CLK_MUX_IOPERI, "clk_mux_ioperi", clk_mux_ioperi_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ARRAY_SIZE(clk_mux_ioperi_p), CLK_SET_RATE_PARENT, 0x108, 10, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct hisi_divider_clock hi3660_crgctrl_divider_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { HI3660_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { HI3660_CLK_DIV_UART1, "clk_div_uart1", "clk_andgt_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { HI3660_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { HI3660_CLK_DIV_MMC, "clk_div_mmc", "clk_andgt_mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { HI3660_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { HI3660_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { HI3660_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { HI3660_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { HI3660_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { HI3660_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { HI3660_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) CLK_SET_RATE_PARENT, 0xc8, 6, 5, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { HI3660_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) CLK_SET_RATE_PARENT, 0xcc, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { HI3660_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_vivobus_andgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { HI3660_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) CLK_SET_RATE_PARENT, 0xe8, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { HI3660_CLK_DIV_UFSPHY, "clk_div_ufsphy_cfg", "clk_gate_ufsphy_gt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) CLK_SET_RATE_PARENT, 0xe8, 9, 2, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { HI3660_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) CLK_SET_RATE_PARENT, 0xec, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { HI3660_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CLK_SET_RATE_PARENT, 0xec, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { HI3660_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) CLK_SET_RATE_PARENT, 0xec, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { HI3660_CLK_DIV_UFSPERI, "clk_div_ufsperi", "clk_gate_ufs_subsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) CLK_SET_RATE_PARENT, 0xec, 14, 1, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { HI3660_CLK_DIV_AOMM, "clk_div_aomm", "clk_aomm_andgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CLK_SET_RATE_PARENT, 0x100, 7, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { HI3660_CLK_DIV_ISP_SNCLK, "clk_isp_snclk_div", "clk_isp_snclk_fac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { HI3660_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_mux_ioperi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) CLK_SET_RATE_PARENT, 0x108, 11, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* clk_pmuctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* pmu register need shift 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct hisi_gate_clock hi3660_pmu_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { HI3660_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) CLK_SET_RATE_PARENT, (0x10a << 2), 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* clk_pctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct hisi_gate_clock hi3660_pctrl_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { HI3660_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "clk_gate_abb_192", CLK_SET_RATE_PARENT, 0x10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { HI3660_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* clk_sctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const struct hisi_gate_clock hi3660_sctrl_gate_sep_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { HI3660_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) CLK_SET_RATE_PARENT, 0x160, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { HI3660_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) CLK_SET_RATE_PARENT, 0x160, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { HI3660_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CLK_SET_RATE_PARENT, 0x160, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { HI3660_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) CLK_SET_RATE_PARENT, 0x160, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { HI3660_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CLK_SET_RATE_PARENT, 0x160, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { HI3660_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) CLK_SET_RATE_PARENT, 0x160, 22, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { HI3660_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) CLK_SET_RATE_PARENT, 0x160, 25, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { HI3660_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) CLK_SET_RATE_PARENT, 0x170, 23, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { HI3660_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "aclk_mux_mmbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) CLK_SET_RATE_PARENT, 0x170, 24, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct hisi_gate_clock hi3660_sctrl_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { HI3660_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "clk_sw_mmbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CLK_SET_RATE_PARENT, 0x258, 7, CLK_GATE_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { HI3660_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CLK_SET_RATE_PARENT, 0x260, 11, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { HI3660_CLK_FLL_MMBUF_ANDGT, "clk_fll_mmbuf_andgt", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) CLK_SET_RATE_PARENT, 0x260, 12, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { HI3660_CLK_SYS_MMBUF_ANDGT, "clk_sys_mmbuf_andgt", "clkin_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) CLK_SET_RATE_PARENT, 0x260, 13, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { HI3660_CLK_GATE_PCIEPHY_GT, "clk_gate_pciephy_gt", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) CLK_SET_RATE_PARENT, 0x268, 11, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) aclk_mux_mmbuf_p[] = {"aclk_div_mmbuf", "clk_gate_aomm",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const char *const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) clk_sw_mmbuf_p[] = {"clk_sys_mmbuf_andgt", "clk_fll_mmbuf_andgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "aclk_mux_mmbuf", "aclk_mux_mmbuf"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct hisi_mux_clock hi3660_sctrl_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { HI3660_ACLK_MUX_MMBUF, "aclk_mux_mmbuf", aclk_mux_mmbuf_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ARRAY_SIZE(aclk_mux_mmbuf_p), CLK_SET_RATE_PARENT, 0x250, 12, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { HI3660_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT, 0x258, 8, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const struct hisi_divider_clock hi3660_sctrl_divider_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { HI3660_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { HI3660_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) CLK_SET_RATE_PARENT, 0x258, 10, 2, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { HI3660_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CLK_SET_RATE_PARENT, 0x258, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { HI3660_CLK_DIV_PCIEPHY, "clk_div_pciephy", "clk_gate_pciephy_gt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) CLK_SET_RATE_PARENT, 0x268, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* clk_iomcu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct hisi_gate_clock hi3660_iomcu_gate_sep_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { HI3660_CLK_I2C0_IOMCU, "clk_i2c0_iomcu", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) CLK_SET_RATE_PARENT, 0x10, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { HI3660_CLK_I2C1_IOMCU, "clk_i2c1_iomcu", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) CLK_SET_RATE_PARENT, 0x10, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { HI3660_CLK_I2C2_IOMCU, "clk_i2c2_iomcu", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) CLK_SET_RATE_PARENT, 0x10, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { HI3660_CLK_I2C6_IOMCU, "clk_i2c6_iomcu", "clk_fll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) CLK_SET_RATE_PARENT, 0x10, 27, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { HI3660_CLK_IOMCU_PERI0, "iomcu_peri0", "clk_ppll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) CLK_SET_RATE_PARENT, 0x90, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct hisi_clock_data *clk_crgctrl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void hi3660_clk_iomcu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void hi3660_clk_pmuctrl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int nr = ARRAY_SIZE(hi3660_pmu_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) hisi_clk_register_gate(hi3660_pmu_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void hi3660_clk_pctrl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hisi_clk_register_gate(hi3660_pctrl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void hi3660_clk_sctrl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ARRAY_SIZE(hi3660_sctrl_mux_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ARRAY_SIZE(hi3660_sctrl_divider_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) clk_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hisi_clk_register_gate(hi3660_sctrl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hisi_clk_register_mux(hi3660_sctrl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) hisi_clk_register_divider(hi3660_sctrl_divider_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ARRAY_SIZE(hi3660_sctrl_divider_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static void hi3660_clk_crgctrl_early_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ARRAY_SIZE(hi3660_crgctrl_gate_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ARRAY_SIZE(hi3660_crgctrl_mux_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ARRAY_SIZE(hi3660_crg_fixed_factor_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ARRAY_SIZE(hi3660_crgctrl_divider_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) clk_crgctrl_data = hisi_clk_init(np, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (!clk_crgctrl_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) for (i = 0; i < nr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) clk_crgctrl_data->clk_data.clks[i] = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ARRAY_SIZE(hi3660_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clk_crgctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) hi3660_clk_crgctrl_early_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void hi3660_clk_crgctrl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!clk_crgctrl_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) hi3660_clk_crgctrl_early_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* clk_crgctrl_data initialization failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!clk_crgctrl_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) clk_crgctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) hisi_clk_register_gate(hi3660_crgctrl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ARRAY_SIZE(hi3660_crgctrl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) clk_crgctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) hisi_clk_register_mux(hi3660_crgctrl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ARRAY_SIZE(hi3660_crgctrl_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk_crgctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ARRAY_SIZE(hi3660_crg_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) clk_crgctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) hisi_clk_register_divider(hi3660_crgctrl_divider_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ARRAY_SIZE(hi3660_crgctrl_divider_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) clk_crgctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) clks = clk_crgctrl_data->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pr_err("Failed to register crgctrl clock[%d] err=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) i, PTR_ERR(clks[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const struct of_device_id hi3660_clk_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { .compatible = "hisilicon,hi3660-crgctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .data = hi3660_clk_crgctrl_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) { .compatible = "hisilicon,hi3660-pctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .data = hi3660_clk_pctrl_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { .compatible = "hisilicon,hi3660-pmuctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .data = hi3660_clk_pmuctrl_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { .compatible = "hisilicon,hi3660-sctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .data = hi3660_clk_sctrl_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { .compatible = "hisilicon,hi3660-iomcu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .data = hi3660_clk_iomcu_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int hi3660_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) void (*init_func)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) init_func = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (!init_func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) init_func(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static struct platform_driver hi3660_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .probe = hi3660_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .name = "hi3660-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .of_match_table = hi3660_clk_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int __init hi3660_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return platform_driver_register(&hi3660_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) core_initcall(hi3660_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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