^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hisilicon clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013-2017 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Kai Zhao <zhaokai1@hisilicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Tao Wang <kevin.wangtao@hisilicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Leo Yan <leo.yan@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mailbox_client.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <dt-bindings/clock/hi3660-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HI3660_STUB_CLOCK_DATA (0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MHZ (1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DEFINE_CLK_STUB(_id, _cmd, _name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .id = (_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .cmd = (_cmd), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .ops = &hi3660_stub_clk_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .num_parents = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .flags = CLK_GET_RATE_NOCACHE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define to_stub_clk(_hw) container_of(_hw, struct hi3660_stub_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct hi3660_stub_clk_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mbox_client cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct mbox_chan *mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct hi3660_stub_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int msg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void __iomem *freq_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct hi3660_stub_clk_chan stub_clk_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static unsigned long hi3660_stub_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * LPM3 writes back the CPU frequency in shared SRAM so read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * back the frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return stub_clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static long hi3660_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * LPM3 handles rate rounding so just return whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * rate is requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int hi3660_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) stub_clk->msg[0] = stub_clk->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) stub_clk->msg[1] = rate / MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_dbg(stub_clk_chan.cl.dev, "set rate msg[0]=0x%x msg[1]=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) stub_clk->msg[0], stub_clk->msg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mbox_send_message(stub_clk_chan.mbox, stub_clk->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mbox_client_txdone(stub_clk_chan.mbox, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) stub_clk->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct clk_ops hi3660_stub_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .recalc_rate = hi3660_stub_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .round_rate = hi3660_stub_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .set_rate = hi3660_stub_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct hi3660_stub_clk hi3660_stub_clks[HI3660_CLK_STUB_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER0, 0x0001030A, "cpu-cluster.0")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER1, 0x0002030A, "cpu-cluster.1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEFINE_CLK_STUB(HI3660_CLK_STUB_DDR, 0x00040309, "clk-ddrc")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (idx >= HI3660_CLK_STUB_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return &hi3660_stub_clks[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int hi3660_stub_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Use mailbox client without blocking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) stub_clk_chan.cl.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) stub_clk_chan.cl.tx_done = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) stub_clk_chan.cl.tx_block = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) stub_clk_chan.cl.knows_txdone = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Allocate mailbox channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (IS_ERR(stub_clk_chan.mbox))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return PTR_ERR(stub_clk_chan.mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) freq_reg = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!freq_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) freq_reg += HI3660_STUB_CLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (i = 0; i < HI3660_CLK_STUB_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return devm_of_clk_add_hw_provider(&pdev->dev, hi3660_stub_clk_hw_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) hi3660_stub_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct of_device_id hi3660_stub_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { .compatible = "hisilicon,hi3660-stub-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct platform_driver hi3660_stub_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .probe = hi3660_stub_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "hi3660-stub-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .of_match_table = hi3660_stub_clk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int __init hi3660_stub_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return platform_driver_register(&hi3660_stub_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) subsys_initcall(hi3660_stub_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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