^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hisilicon Hi3620 clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012-2013 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2012-2013 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xin Li <li.xin@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/clock/hi3620-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* clock parent list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const char *const timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const char *const timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const char *const timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const char *const timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const char *const timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const char *const timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const char *const timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const char *const timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char *const timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const char *const timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const char *const spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const char *const spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char *const spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* share axi parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char *const saxi_mux_p[] __initconst = { "armpll3", "armpll2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const char *const pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char *const pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char *const sd_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const char *const mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const char *const mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const char *const g2d_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char *const venc_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const char *const vdec_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const char *const vpp_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const char *const edc0_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char *const ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "armpll3", "armpll5", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const char *const edc1_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const char *const ldi1_mux_p[] __initconst = { "armpll2", "armpll4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "armpll3", "armpll5", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const char *const rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const char *const mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const char *const mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { HI3620_OSC32K, "osc32k", NULL, 0, 32768, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { HI3620_OSC26M, "osc26m", NULL, 0, 26000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { HI3620_PCLK, "pclk", NULL, 0, 26000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { HI3620_PLL_ARM0, "armpll0", NULL, 0, 1600000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { HI3620_PLL_ARM1, "armpll1", NULL, 0, 1600000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { HI3620_PLL_PERI, "armpll2", NULL, 0, 1440000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { HI3620_PLL_USB, "armpll3", NULL, 0, 1440000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { HI3620_PLL_HDMI, "armpll4", NULL, 0, 1188000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { HI3620_PLL_GPU, "armpll5", NULL, 0, 1300000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* fixed factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { HI3620_RCLK_CFGAXI, "rclk_cfgaxi", "armpll2", 1, 30, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { HI3620_RCLK_PICO, "rclk_pico", "hsic_div", 1, 40, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct hisi_mux_clock hi3620_mux_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0, 15, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0, 17, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0, 19, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0, 21, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x18, 0, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x18, 2, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x18, 4, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x18, 6, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x18, 8, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x18, 10, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { HI3620_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { HI3620_UART1_MUX, "uart1_mux", uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { HI3620_UART2_MUX, "uart2_mux", uart2_mux_p, ARRAY_SIZE(uart2_mux_p), CLK_SET_RATE_PARENT, 0x100, 9, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { HI3620_UART3_MUX, "uart3_mux", uart3_mux_p, ARRAY_SIZE(uart3_mux_p), CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { HI3620_UART4_MUX, "uart4_mux", uart4_mux_p, ARRAY_SIZE(uart4_mux_p), CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { HI3620_SPI0_MUX, "spi0_mux", spi0_mux_p, ARRAY_SIZE(spi0_mux_p), CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { HI3620_SPI1_MUX, "spi1_mux", spi1_mux_p, ARRAY_SIZE(spi1_mux_p), CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { HI3620_SPI2_MUX, "spi2_mux", spi2_mux_p, ARRAY_SIZE(spi2_mux_p), CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { HI3620_SAXI_MUX, "saxi_mux", saxi_mux_p, ARRAY_SIZE(saxi_mux_p), CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { HI3620_PWM0_MUX, "pwm0_mux", pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { HI3620_PWM1_MUX, "pwm1_mux", pwm1_mux_p, ARRAY_SIZE(pwm1_mux_p), CLK_SET_RATE_PARENT, 0x104, 11, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { HI3620_SD_MUX, "sd_mux", sd_mux_p, ARRAY_SIZE(sd_mux_p), CLK_SET_RATE_PARENT, 0x108, 4, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { HI3620_MMC1_MUX, "mmc1_mux", mmc1_mux_p, ARRAY_SIZE(mmc1_mux_p), CLK_SET_RATE_PARENT, 0x108, 9, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { HI3620_MMC1_MUX2, "mmc1_mux2", mmc1_mux2_p, ARRAY_SIZE(mmc1_mux2_p), CLK_SET_RATE_PARENT, 0x108, 10, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { HI3620_G2D_MUX, "g2d_mux", g2d_mux_p, ARRAY_SIZE(g2d_mux_p), CLK_SET_RATE_PARENT, 0x10c, 5, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { HI3620_VENC_MUX, "venc_mux", venc_mux_p, ARRAY_SIZE(venc_mux_p), CLK_SET_RATE_PARENT, 0x10c, 11, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { HI3620_VDEC_MUX, "vdec_mux", vdec_mux_p, ARRAY_SIZE(vdec_mux_p), CLK_SET_RATE_PARENT, 0x110, 5, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { HI3620_VPP_MUX, "vpp_mux", vpp_mux_p, ARRAY_SIZE(vpp_mux_p), CLK_SET_RATE_PARENT, 0x110, 11, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { HI3620_EDC0_MUX, "edc0_mux", edc0_mux_p, ARRAY_SIZE(edc0_mux_p), CLK_SET_RATE_PARENT, 0x114, 6, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { HI3620_LDI0_MUX, "ldi0_mux", ldi0_mux_p, ARRAY_SIZE(ldi0_mux_p), CLK_SET_RATE_PARENT, 0x114, 13, 2, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { HI3620_EDC1_MUX, "edc1_mux", edc1_mux_p, ARRAY_SIZE(edc1_mux_p), CLK_SET_RATE_PARENT, 0x118, 6, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { HI3620_LDI1_MUX, "ldi1_mux", ldi1_mux_p, ARRAY_SIZE(ldi1_mux_p), CLK_SET_RATE_PARENT, 0x118, 14, 2, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { HI3620_RCLK_HSIC, "rclk_hsic", rclk_hsic_p, ARRAY_SIZE(rclk_hsic_p), CLK_SET_RATE_PARENT, 0x130, 2, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { HI3620_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p), CLK_SET_RATE_PARENT, 0x140, 4, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct hisi_divider_clock hi3620_div_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { HI3620_TIMER_RCLK23, "timer_rclk23", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { HI3620_GPIOCLK2, "gpioclk2", "pclk", CLK_SET_RATE_PARENT, 0x20, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { HI3620_GPIOCLK3, "gpioclk3", "pclk", CLK_SET_RATE_PARENT, 0x20, 11, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { HI3620_GPIOCLK4, "gpioclk4", "pclk", CLK_SET_RATE_PARENT, 0x20, 12, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { HI3620_GPIOCLK5, "gpioclk5", "pclk", CLK_SET_RATE_PARENT, 0x20, 13, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { HI3620_GPIOCLK6, "gpioclk6", "pclk", CLK_SET_RATE_PARENT, 0x20, 14, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { HI3620_GPIOCLK7, "gpioclk7", "pclk", CLK_SET_RATE_PARENT, 0x20, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { HI3620_GPIOCLK8, "gpioclk8", "pclk", CLK_SET_RATE_PARENT, 0x20, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { HI3620_GPIOCLK9, "gpioclk9", "pclk", CLK_SET_RATE_PARENT, 0x20, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { HI3620_GPIOCLK10, "gpioclk10", "pclk", CLK_SET_RATE_PARENT, 0x20, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { HI3620_GPIOCLK11, "gpioclk11", "pclk", CLK_SET_RATE_PARENT, 0x20, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { HI3620_GPIOCLK12, "gpioclk12", "pclk", CLK_SET_RATE_PARENT, 0x20, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { HI3620_GPIOCLK13, "gpioclk13", "pclk", CLK_SET_RATE_PARENT, 0x20, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { HI3620_GPIOCLK14, "gpioclk14", "pclk", CLK_SET_RATE_PARENT, 0x20, 22, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { HI3620_GPIOCLK15, "gpioclk15", "pclk", CLK_SET_RATE_PARENT, 0x20, 23, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { HI3620_GPIOCLK16, "gpioclk16", "pclk", CLK_SET_RATE_PARENT, 0x20, 24, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { HI3620_GPIOCLK17, "gpioclk17", "pclk", CLK_SET_RATE_PARENT, 0x20, 25, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { HI3620_GPIOCLK18, "gpioclk18", "pclk", CLK_SET_RATE_PARENT, 0x20, 26, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { HI3620_GPIOCLK19, "gpioclk19", "pclk", CLK_SET_RATE_PARENT, 0x20, 27, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { HI3620_GPIOCLK20, "gpioclk20", "pclk", CLK_SET_RATE_PARENT, 0x20, 28, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { HI3620_GPIOCLK21, "gpioclk21", "pclk", CLK_SET_RATE_PARENT, 0x20, 29, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { HI3620_DPHY0_CLK, "dphy0_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 15, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { HI3620_DPHY1_CLK, "dphy1_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { HI3620_DPHY2_CLK, "dphy2_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { HI3620_USBPHY_CLK, "usbphy_clk", "rclk_pico", CLK_SET_RATE_PARENT, 0x30, 24, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { HI3620_ACP_CLK, "acp_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x30, 28, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { HI3620_TIMERCLK45, "timerclk45", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 3, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { HI3620_TIMERCLK67, "timerclk67", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 4, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { HI3620_TIMERCLK89, "timerclk89", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 5, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { HI3620_PWMCLK0, "pwmclk0", "pwm0_mux", CLK_SET_RATE_PARENT, 0x40, 7, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { HI3620_PWMCLK1, "pwmclk1", "pwm1_mux", CLK_SET_RATE_PARENT, 0x40, 8, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { HI3620_UARTCLK0, "uartclk0", "uart0_mux", CLK_SET_RATE_PARENT, 0x40, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { HI3620_UARTCLK1, "uartclk1", "uart1_mux", CLK_SET_RATE_PARENT, 0x40, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { HI3620_UARTCLK2, "uartclk2", "uart2_mux", CLK_SET_RATE_PARENT, 0x40, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { HI3620_UARTCLK3, "uartclk3", "uart3_mux", CLK_SET_RATE_PARENT, 0x40, 19, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { HI3620_UARTCLK4, "uartclk4", "uart4_mux", CLK_SET_RATE_PARENT, 0x40, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { HI3620_SPICLK0, "spiclk0", "spi0_mux", CLK_SET_RATE_PARENT, 0x40, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { HI3620_SPICLK1, "spiclk1", "spi1_mux", CLK_SET_RATE_PARENT, 0x40, 22, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { HI3620_SPICLK2, "spiclk2", "spi2_mux", CLK_SET_RATE_PARENT, 0x40, 23, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { HI3620_I2CCLK0, "i2cclk0", "pclk", CLK_SET_RATE_PARENT, 0x40, 24, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { HI3620_I2CCLK1, "i2cclk1", "pclk", CLK_SET_RATE_PARENT, 0x40, 25, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { HI3620_SCI_CLK, "sci_clk", "osc26m", CLK_SET_RATE_PARENT, 0x40, 26, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { HI3620_I2CCLK2, "i2cclk2", "pclk", CLK_SET_RATE_PARENT, 0x40, 28, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { HI3620_I2CCLK3, "i2cclk3", "pclk", CLK_SET_RATE_PARENT, 0x40, 29, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { HI3620_DDRC_PER_CLK, "ddrc_per_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 9, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { HI3620_DMAC_CLK, "dmac_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 10, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { HI3620_USB2DVC_CLK, "usb2dvc_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { HI3620_SD_CLK, "sd_clk", "sd_div", CLK_SET_RATE_PARENT, 0x50, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { HI3620_MMC_CLK1, "mmc_clk1", "mmc1_mux2", CLK_SET_RATE_PARENT, 0x50, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { HI3620_MMC_CLK2, "mmc_clk2", "mmc2_div", CLK_SET_RATE_PARENT, 0x50, 22, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { HI3620_MMC_CLK3, "mmc_clk3", "mmc3_div", CLK_SET_RATE_PARENT, 0x50, 23, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PARENT, 0x50, 24, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void __init hi3620_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_data = hisi_clk_init(np, HI3620_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ARRAY_SIZE(hi3620_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ARRAY_SIZE(hi3620_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) hisi_clk_register_gate_sep(hi3620_separated_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ARRAY_SIZE(hi3620_separated_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct hisi_mmc_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 clken_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 clken_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 div_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 div_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 drv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 drv_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 drv_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 sam_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 sam_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 sam_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct clk_mmc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void __iomem *clken_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 clken_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void __iomem *div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 div_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 div_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void __iomem *drv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 drv_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 drv_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __iomem *sam_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 sam_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 sam_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define to_mmc(_hw) container_of(_hw, struct clk_mmc, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct hisi_mmc_clock hi3620_mmc_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { HI3620_SD_CIUCLK, "sd_bclk1", "sd_clk", CLK_SET_RATE_PARENT, 0x1f8, 0, 0x1f8, 1, 3, 0x1f8, 4, 4, 0x1f8, 8, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { HI3620_MMC_CIUCLK1, "mmc_bclk1", "mmc_clk1", CLK_SET_RATE_PARENT, 0x1f8, 12, 0x1f8, 13, 3, 0x1f8, 16, 4, 0x1f8, 20, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { HI3620_MMC_CIUCLK2, "mmc_bclk2", "mmc_clk2", CLK_SET_RATE_PARENT, 0x1f8, 24, 0x1f8, 25, 3, 0x1f8, 28, 4, 0x1fc, 0, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { HI3620_MMC_CIUCLK3, "mmc_bclk3", "mmc_clk3", CLK_SET_RATE_PARENT, 0x1fc, 4, 0x1fc, 5, 3, 0x1fc, 8, 4, 0x1fc, 12, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) switch (parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case 180000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case 360000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case 720000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case 1440000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 180000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int mmc_clk_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct clk_mmc *mclk = to_mmc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) req->rate = 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) req->best_parent_rate = 26000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else if (req->rate <= 26000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) req->rate = 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) req->best_parent_rate = 180000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) } else if (req->rate <= 52000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) req->rate = 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) req->best_parent_rate = 360000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else if (req->rate <= 100000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) req->rate = 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) req->best_parent_rate = 720000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* max is 180M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) req->rate = 180000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) req->best_parent_rate = 1440000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static u32 mmc_clk_delay(u32 val, u32 para, u32 off, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (para % 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val |= 1 << (off + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val &= ~(1 << (off + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) para = para >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int mmc_clk_set_timing(struct clk_hw *hw, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct clk_mmc *mclk = to_mmc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 sam, drv, div, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static DEFINE_SPINLOCK(mmc_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case 13000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) sam = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) drv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case 25000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) sam = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) drv = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case 50000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) sam = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) drv = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case 100000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) sam = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) drv = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case 180000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) sam = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) drv = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) div = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spin_lock_irqsave(&mmc_clk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) val = readl_relaxed(mclk->clken_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val &= ~(1 << mclk->clken_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) writel_relaxed(val, mclk->clken_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) val = readl_relaxed(mclk->sam_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel_relaxed(val, mclk->sam_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) val = readl_relaxed(mclk->drv_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) val = mmc_clk_delay(val, drv, mclk->drv_off, mclk->drv_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) writel_relaxed(val, mclk->drv_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val = readl_relaxed(mclk->div_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) val = mmc_clk_delay(val, div, mclk->div_off, mclk->div_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel_relaxed(val, mclk->div_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) val = readl_relaxed(mclk->clken_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val |= 1 << mclk->clken_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel_relaxed(val, mclk->clken_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) spin_unlock_irqrestore(&mmc_clk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int mmc_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct clk_mmc *mclk = to_mmc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (mclk->id == HI3620_MMC_CIUCLK1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) rate = 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) rate = 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return mmc_clk_set_timing(hw, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int mmc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return mmc_clk_set_timing(hw, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct clk_ops clk_mmc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .prepare = mmc_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .determine_rate = mmc_clk_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .set_rate = mmc_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .recalc_rate = mmc_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) void __iomem *base, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct clk_mmc *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!mclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) init.name = mmc_clk->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) init.ops = &clk_mmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) init.flags = mmc_clk->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) init.parent_names = (mmc_clk->parent_name ? &mmc_clk->parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) init.num_parents = (mmc_clk->parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mclk->id = mmc_clk->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mclk->clken_reg = base + mmc_clk->clken_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mclk->clken_bit = mmc_clk->clken_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mclk->div_reg = base + mmc_clk->div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mclk->div_off = mmc_clk->div_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mclk->div_bits = mmc_clk->div_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mclk->drv_reg = base + mmc_clk->drv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mclk->drv_off = mmc_clk->drv_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mclk->drv_bits = mmc_clk->drv_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) mclk->sam_reg = base + mmc_clk->sam_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mclk->sam_off = mmc_clk->sam_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mclk->sam_bits = mmc_clk->sam_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clk = clk_register(NULL, &mclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (WARN_ON(IS_ERR(clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) kfree(mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void __init hi3620_mmc_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int i, num = ARRAY_SIZE(hi3620_mmc_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pr_err("failed to find pctrl node in DTS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pr_err("failed to map pctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (WARN_ON(!clk_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) clk_data->clks = kcalloc(num, sizeof(*clk_data->clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!clk_data->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct hisi_mmc_clock *mmc_clk = &hi3620_mmc_clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) clk_data->clks[mmc_clk->id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) hisi_register_clk_mmc(mmc_clk, base, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clk_data->clk_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) CLK_OF_DECLARE(hi3620_mmc_clk, "hisilicon,hi3620-mmc-clock", hi3620_mmc_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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