^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hi3519 Clock Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <dt-bindings/clock/hi3519-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HI3519_INNER_CLK_OFFSET 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HI3519_FIXED_24M 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HI3519_FIXED_50M 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HI3519_FIXED_75M 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HI3519_FIXED_125M 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HI3519_FIXED_150M 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HI3519_FIXED_200M 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HI3519_FIXED_250M 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HI3519_FIXED_300M 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HI3519_FIXED_400M 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HI3519_FMC_MUX 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HI3519_NR_CLKS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct hi3519_crg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct hisi_reset_controller *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { HI3519_FIXED_24M, "24m", NULL, 0, 24000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { HI3519_FIXED_50M, "50m", NULL, 0, 50000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { HI3519_FIXED_75M, "75m", NULL, 0, 75000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { HI3519_FIXED_125M, "125m", NULL, 0, 125000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { HI3519_FIXED_150M, "150m", NULL, 0, 150000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { HI3519_FIXED_200M, "200m", NULL, 0, 200000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { HI3519_FIXED_250M, "250m", NULL, 0, 250000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { HI3519_FIXED_300M, "300m", NULL, 0, 300000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { HI3519_FIXED_400M, "400m", NULL, 0, 400000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char *const fmc_mux_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct hisi_mux_clock hi3519_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct hisi_gate_clock hi3519_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { HI3519_UART0_CLK, "clk_uart0", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { HI3519_UART1_CLK, "clk_uart1", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { HI3519_UART2_CLK, "clk_uart2", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { HI3519_UART3_CLK, "clk_uart3", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { HI3519_UART4_CLK, "clk_uart4", "24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { HI3519_SPI0_CLK, "clk_spi0", "50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { HI3519_SPI1_CLK, "clk_spi1", "50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { HI3519_SPI2_CLK, "clk_spi2", "50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct hisi_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk_data = hisi_clk_alloc(pdev, HI3519_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ARRAY_SIZE(hi3519_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = hisi_clk_register_mux(hi3519_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ARRAY_SIZE(hi3519_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) goto unregister_fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = hisi_clk_register_gate(hi3519_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ARRAY_SIZE(hi3519_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) goto unregister_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = of_clk_add_provider(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) of_clk_src_onecell_get, &clk_data->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) goto unregister_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unregister_fixed_rate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ARRAY_SIZE(hi3519_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unregister_mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) hisi_clk_unregister_mux(hi3519_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ARRAY_SIZE(hi3519_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unregister_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) hisi_clk_unregister_gate(hi3519_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ARRAY_SIZE(hi3519_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void hi3519_clk_unregister(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) hisi_clk_unregister_gate(hi3519_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ARRAY_SIZE(hi3519_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) hisi_clk_unregister_mux(hi3519_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ARRAY_SIZE(hi3519_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ARRAY_SIZE(hi3519_fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int hi3519_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct hi3519_crg_data *crg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!crg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) crg->rstc = hisi_reset_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!crg->rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) crg->clk_data = hi3519_clk_register(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (IS_ERR(crg->clk_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) hisi_reset_exit(crg->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return PTR_ERR(crg->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) platform_set_drvdata(pdev, crg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int hi3519_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) hisi_reset_exit(crg->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) hi3519_clk_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct of_device_id hi3519_clk_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .compatible = "hisilicon,hi3519-crg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MODULE_DEVICE_TABLE(of, hi3519_clk_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct platform_driver hi3519_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .probe = hi3519_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .remove = hi3519_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "hi3519-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .of_match_table = hi3519_clk_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int __init hi3519_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return platform_driver_register(&hi3519_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) core_initcall(hi3519_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void __exit hi3519_clk_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) platform_driver_unregister(&hi3519_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) module_exit(hi3519_clk_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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