^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * H8S2678 clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static DEFINE_SPINLOCK(clklock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MAX_FREQ 33333333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MIN_FREQ 8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct pll_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void __iomem *sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void __iomem *pllcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static unsigned long pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct pll_clock *pll_clock = to_pll_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int mul = 1 << (readb(pll_clock->pllcr) & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return parent_rate * mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int i, m = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) long offset[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (rate > MAX_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) rate = MAX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (rate < MIN_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) rate = MIN_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) offset[i] = abs(rate - (*prate * (1 << i)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (m < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) m = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) m = (offset[i] < offset[m])?i:m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return *prate * (1 << m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pll_clock *pll_clock = to_pll_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pll = ((rate / parent_rate) / 2) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) spin_lock_irqsave(&clklock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) val = readb(pll_clock->sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) val |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writeb(val, pll_clock->sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val = readb(pll_clock->pllcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val |= pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writeb(val, pll_clock->pllcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) spin_unlock_irqrestore(&clklock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct clk_ops pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .recalc_rate = pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .round_rate = pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .set_rate = pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void __init h8s2678_pll_clk_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pll_clock *pll_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) num_parents = of_clk_get_parent_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!num_parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_err("%s: no parent found\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!pll_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pll_clock->sckcr = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (pll_clock->sckcr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pr_err("%s: failed to map divide register\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) goto free_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pll_clock->pllcr = of_iomap(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (pll_clock->pllcr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pr_err("%s: failed to map multiply register\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) goto unmap_sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) init.ops = &pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pll_clock->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = clk_hw_register(NULL, &pll_clock->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pr_err("%s: failed to register %s div clock (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __func__, clk_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) goto unmap_pllcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unmap_pllcr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) iounmap(pll_clock->pllcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unmap_sckcr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) iounmap(pll_clock->sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) free_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) kfree(pll_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) h8s2678_pll_clk_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags