Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * H8/300 divide clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static DEFINE_SPINLOCK(clklock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static void __init h8300_div_clk_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	void __iomem *divcr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	num_parents = of_clk_get_parent_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	if (!num_parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		pr_err("%s: no parent found\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	divcr = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	if (divcr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		pr_err("%s: failed to map divide register\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	offset = (unsigned long)divcr & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	offset = (3 - offset) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	divcr = (void __iomem *)((unsigned long)divcr & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	of_property_read_u32(node, "renesas,width", &width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	hw = clk_hw_register_divider(NULL, clk_name, parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 				   CLK_SET_RATE_GATE, divcr, offset, width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 				   CLK_DIVIDER_POWER_OF_TWO, &clklock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	if (!IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	pr_err("%s: failed to register %s div clock (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	       __func__, clk_name, PTR_ERR(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	if (divcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		iounmap(divcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup);