^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PSC clock descriptions for TI DaVinci DM365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "psc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) LPSC_CLKDEV1(asp0_clkdev, NULL, "davinci-mcbsp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) LPSC_CLKDEV2(aemif_clkdev, "aemif", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) NULL, "ti-aemif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* REVISIT: gpio-davinci.c should be modified to drop con_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) LPSC_CLKDEV1(spi3_clkdev, NULL, "spi_davinci.3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) LPSC_CLKDEV1(spi4_clkdev, NULL, "spi_davinci.4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "fck", "davinci_mdio.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) LPSC_CLKDEV1(voice_codec_clkdev, NULL, "davinci_voicecodec");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) LPSC_CLKDEV1(vpss_dac_clkdev, "vpss_dac", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) LPSC(1, 0, vpss_slave, pll1_sysclk5, vpss_slave_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) LPSC(5, 0, timer3, pll1_auxclk, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) LPSC(6, 0, spi1, pll1_sysclk4, spi1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) LPSC(7, 0, mmcsd1, pll1_sysclk4, mmcsd1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) LPSC(8, 0, asp0, pll1_sysclk4, asp0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) LPSC(9, 0, usb, pll1_auxclk, usb_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) LPSC(10, 0, pwm3, pll1_auxclk, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) LPSC(11, 0, spi2, pll1_sysclk4, spi2_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) LPSC(12, 0, rto, pll1_sysclk4, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) LPSC(14, 0, aemif, pll1_sysclk4, aemif_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) LPSC(15, 0, mmcsd0, pll1_sysclk8, mmcsd0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) LPSC(20, 0, uart1, pll1_sysclk4, uart1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) LPSC(22, 0, spi0, pll1_sysclk4, spi0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) LPSC(26, 0, gpio, pll1_sysclk4, gpio_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* REVISIT: why can't this be disabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) LPSC(31, 0, arm, pll2_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) LPSC(38, 0, spi3, pll1_sysclk4, spi3_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) LPSC(39, 0, spi4, pll1_auxclk, spi4_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) LPSC(40, 0, emac, pll1_sysclk4, emac_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * The TRM (ARM Subsystem User's Guide) shows two clocks input into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * voice codec module (PLL2 SYSCLK4 with a DIV2 and PLL1 SYSCLK4). Its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * not fully clear from documentation which clock should be considered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * as parent for PSC. The clock chosen here is to maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * compatibility with existing code in arch/arm/mach-davinci/dm365.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) LPSC(44, 0, voice_codec, pll2_sysclk4, voice_codec_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Its not fully clear from TRM (ARM Subsystem User's Guide) as to what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * the parent of VPSS DAC LPSC should actually be. PLL1 SYSCLK3 feeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * into HDVICP and MJCP. The clock chosen here is to remain compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * with code existing in arch/arm/mach-davinci/dm365.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) LPSC(46, 0, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) LPSC(50, 0, mjcp, pll1_sysclk3, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int dm365_psc_init(struct device *dev, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return davinci_psc_register_clocks(dev, dm365_psc_info, 52, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct clk_bulk_data dm365_psc_parent_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .id = "pll1_sysclk1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .id = "pll1_sysclk3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .id = "pll1_sysclk4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { .id = "pll1_sysclk5" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .id = "pll1_sysclk8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .id = "pll2_sysclk2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .id = "pll2_sysclk4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .id = "pll1_auxclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct davinci_psc_init_data dm365_psc_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .parent_clks = dm365_psc_parent_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .num_parent_clks = ARRAY_SIZE(dm365_psc_parent_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .psc_init = &dm365_psc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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