^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PSC clock descriptions for TI DA850/OMAP-L138/AM18XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "psc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) LPSC_CLKDEV1(emifa_clkdev, NULL, "ti-aemif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* REVISIT: used dev_id instead of con_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) LPSC_CLKDEV1(arm_clkdev, "arm", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) LPSC_CLKDEV1(dsp_clkdev, NULL, "davinci-rproc.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const struct davinci_lpsc_clk_info da850_psc0_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) LPSC(0, 0, tpcc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) LPSC(3, 0, emifa, async1, emifa_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) LPSC(5, 0, mmcsd0, pll0_sysclk2, mmcsd0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) LPSC(13, 0, pruss, pll0_sysclk2, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) LPSC(14, 0, arm, pll0_sysclk6, arm_clkdev, LPSC_ALWAYS_ENABLED | LPSC_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) LPSC(15, 1, dsp, pll0_sysclk1, dsp_clkdev, LPSC_FORCE | LPSC_LOCAL_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) NULL, "musb-da8xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) NULL, "cppi41-dmaengine");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* REVISIT: gpio-davinci.c should be modified to drop con_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "fck", "davinci_mdio.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) LPSC_CLKDEV1(sata_clkdev, "fck", "ahci_da850");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) LPSC_CLKDEV1(vpif_clkdev, NULL, "vpif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) LPSC_CLKDEV1(mcbsp0_clkdev, NULL, "davinci-mcbsp.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) LPSC_CLKDEV1(mcbsp1_clkdev, NULL, "davinci-mcbsp.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) LPSC_CLKDEV3(ehrpwm_clkdev, "fck", "ehrpwm.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "fck", "ehrpwm.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) NULL, "da830-tbclksync");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "fck", "ecap.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "fck", "ecap.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct reset_control_lookup da850_psc0_reset_lookup_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RESET_LOOKUP("da850-psc0", 15, "davinci-rproc.0", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int da850_psc0_init(struct device *dev, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reset_controller_add_lookup(da850_psc0_reset_lookup_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ARRAY_SIZE(da850_psc0_reset_lookup_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return davinci_psc_register_clocks(dev, da850_psc0_info, 16, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int of_da850_psc0_init(struct device *dev, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return of_davinci_psc_clk_init(dev, da850_psc0_info, 16, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct clk_bulk_data da850_psc0_parent_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { .id = "pll0_sysclk1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { .id = "pll0_sysclk2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .id = "pll0_sysclk4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .id = "pll0_sysclk6" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { .id = "async1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const struct davinci_psc_init_data da850_psc0_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .parent_clks = da850_psc0_parent_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .psc_init = &da850_psc0_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const struct davinci_psc_init_data of_da850_psc0_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .parent_clks = da850_psc0_parent_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .psc_init = &of_da850_psc0_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct davinci_lpsc_clk_info da850_psc1_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) LPSC(0, 0, tpcc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) LPSC(6, 0, ddr, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) LPSC(7, 0, mcasp0, async3, mcasp0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) LPSC(8, 0, sata, pll0_sysclk2, sata_clkdev, LPSC_FORCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) LPSC(9, 0, vpif, pll0_sysclk2, vpif_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) LPSC(10, 0, spi1, async3, spi1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) LPSC(12, 0, uart1, async3, uart1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) LPSC(13, 0, uart2, async3, uart2_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) LPSC(14, 0, mcbsp0, async3, mcbsp0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) LPSC(15, 0, mcbsp1, async3, mcbsp1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) LPSC(17, 0, ehrpwm, async3, ehrpwm_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) LPSC(18, 0, mmcsd1, pll0_sysclk2, mmcsd1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) LPSC(20, 0, ecap, async3, ecap_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) LPSC(21, 0, tptc2, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int da850_psc1_init(struct device *dev, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return davinci_psc_register_clocks(dev, da850_psc1_info, 32, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int of_da850_psc1_init(struct device *dev, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return of_davinci_psc_clk_init(dev, da850_psc1_info, 32, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct clk_bulk_data da850_psc1_parent_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .id = "pll0_sysclk2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .id = "pll0_sysclk4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .id = "async3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct davinci_psc_init_data da850_psc1_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .parent_clks = da850_psc1_parent_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .psc_init = &da850_psc1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const struct davinci_psc_init_data of_da850_psc1_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .parent_clks = da850_psc1_parent_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .psc_init = &of_da850_psc1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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