^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PSC clock descriptions for TI DA830/OMAP-L137/AM17XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "psc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) LPSC_CLKDEV1(aemif_clkdev, NULL, "ti-aemif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) LPSC_CLKDEV1(mmcsd_clkdev, NULL, "da830-mmc.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct davinci_lpsc_clk_info da830_psc0_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) LPSC(0, 0, tpcc, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) LPSC(3, 0, aemif, pll0_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) LPSC(5, 0, mmcsd, pll0_sysclk2, mmcsd_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) LPSC(8, 0, secu_mgr, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) LPSC(10, 0, scr0_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) LPSC(11, 0, scr1_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) LPSC(12, 0, scr2_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) LPSC(13, 0, pruss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) LPSC(14, 0, arm, pll0_sysclk6, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int da830_psc0_init(struct device *dev, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return davinci_psc_register_clocks(dev, da830_psc0_info, 16, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct clk_bulk_data da830_psc0_parent_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .id = "pll0_sysclk2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { .id = "pll0_sysclk3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { .id = "pll0_sysclk4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { .id = "pll0_sysclk6" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const struct davinci_psc_init_data da830_psc0_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .parent_clks = da830_psc0_parent_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .num_parent_clks = ARRAY_SIZE(da830_psc0_parent_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .psc_init = &da830_psc0_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) NULL, "musb-da8xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) NULL, "cppi41-dmaengine");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* REVISIT: gpio-davinci.c should be modified to drop con_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "fck", "davinci_mdio.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) LPSC_CLKDEV1(mcasp2_clkdev, NULL, "davinci-mcasp.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) LPSC_CLKDEV2(pwm_clkdev, "fck", "ehrpwm.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "fck", "ehrpwm.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "fck", "ecap.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "fck", "ecap.2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) LPSC_CLKDEV2(eqep_clkdev, NULL, "eqep.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) NULL, "eqep.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct davinci_lpsc_clk_info da830_psc1_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) LPSC(6, 0, emif3, pll0_sysclk5, NULL, LPSC_ALWAYS_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) LPSC(7, 0, mcasp0, pll0_sysclk2, mcasp0_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) LPSC(8, 0, mcasp1, pll0_sysclk2, mcasp1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) LPSC(9, 0, mcasp2, pll0_sysclk2, mcasp2_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) LPSC(10, 0, spi1, pll0_sysclk2, spi1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) LPSC(12, 0, uart1, pll0_sysclk2, uart1_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) LPSC(13, 0, uart2, pll0_sysclk2, uart2_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) LPSC(17, 0, pwm, pll0_sysclk2, pwm_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LPSC(20, 0, ecap, pll0_sysclk2, ecap_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LPSC(21, 0, eqep, pll0_sysclk2, eqep_clkdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int da830_psc1_init(struct device *dev, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return davinci_psc_register_clocks(dev, da830_psc1_info, 32, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct clk_bulk_data da830_psc1_parent_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .id = "pll0_sysclk2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .id = "pll0_sysclk4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .id = "pll0_sysclk5" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct davinci_psc_init_data da830_psc1_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .parent_clks = da830_psc1_parent_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .num_parent_clks = ARRAY_SIZE(da830_psc1_parent_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .psc_init = &da830_psc1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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