^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Clock driver for TI Davinci PSC controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __CLK_DAVINCI_PLL_H___
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __CLK_DAVINCI_PLL_H___
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL_PREDIV_ALWAYS_ENABLED BIT(2) /* don't clear DEN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_POSTDIV_ALWAYS_ENABLED BIT(5) /* don't clear DEN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_HAS_EXTCLKSRC BIT(7) /* has selectable bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_PLLM_2X BIT(8) /* PLLM value is 2x (DM365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLL_PREDIV_FIXED8 BIT(9) /* DM355 quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /** davinci_pll_clk_info - controller-specific PLL info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @name: The name of the PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @unlock_reg: Option CFGCHIP register for unlocking PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @unlock_mask: Bitmask used with @unlock_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @pllm_mask: Bitmask for PLLM[PLLM] value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @pllm_min: Minimum allowable value for PLLM[PLLM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @pllm_max: Maximum allowable value for PLLM[PLLM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @pllout_min_rate: Minimum allowable rate for PLLOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @pllout_max_rate: Maximum allowable rate for PLLOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @flags: Bitmap of PLL_* flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct davinci_pll_clk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 unlock_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 unlock_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 pllm_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 pllm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 pllm_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long pllout_min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long pllout_max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SYSCLK_ALWAYS_ENABLED BIT(1) /* Or bad things happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /** davinci_pll_sysclk_info - SYSCLKn-specific info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @name: The name of the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @parent_name: The name of the parent clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @id: "n" in "SYSCLKn"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @ratio_width: Width (in bits) of RATIO in PLLDIVn register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @flags: Bitmap of SYSCLK_* flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct davinci_pll_sysclk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 ratio_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SYSCLK(i, n, p, w, f) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct davinci_pll_sysclk_info n = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = #n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .parent_name = #p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .id = (i), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .ratio_width = (w), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .flags = (f), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /** davinci_pll_obsclk_info - OBSCLK-specific info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @name: The name of the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @parent_names: Array of names of the parent clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @num_parents: Length of @parent_names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @table: Array of values to write to OCSEL[OCSRC] cooresponding to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @parent_names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @ocsrc_mask: Bitmask for OCSEL[OCSRC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct davinci_pll_obsclk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 ocsrc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk *davinci_pll_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const struct davinci_pll_clk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct regmap *cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct clk *davinci_pll_auxclk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) davinci_pll_obsclk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct davinci_pll_obsclk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) davinci_pll_sysclk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) const struct davinci_pll_sysclk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int of_davinci_pll_init(struct device *dev, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const struct davinci_pll_clk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const struct davinci_pll_obsclk_info *obsclk_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const struct davinci_pll_sysclk_info **div_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 max_sysclk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct regmap *cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Platform-specific callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #ifdef CONFIG_ARCH_DAVINCI_DA850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void of_da850_pll0_init(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_ARCH_DAVINCI_DM355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifdef CONFIG_ARCH_DAVINCI_DM644x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef CONFIG_ARCH_DAVINCI_DM646x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif /* __CLK_DAVINCI_PLL_H___ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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