Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * PLL clock descriptions for TI DM644X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const struct davinci_pll_clk_info dm644x_pll1_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.name = "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	.pllm_mask = GENMASK(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	.pllm_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	.pllm_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.pllout_min_rate = 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.pllout_max_rate = 600000000, /* 810MHz @ 1.3V, -810 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.flags = PLL_HAS_CLKMODE | PLL_HAS_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	clk_register_clkdev(clk, "pll1_sysclk2", "dm644x-psc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	clk_register_clkdev(clk, "pll1_sysclk3", "dm644x-psc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	clk_register_clkdev(clk, "pll1_sysclk5", "dm644x-psc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	clk_register_clkdev(clk, "pll1_auxclk", "dm644x-psc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct davinci_pll_clk_info dm644x_pll2_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	.name = "pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	.pllm_mask = GENMASK(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	.pllm_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	.pllm_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	.pllout_min_rate = 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	.pllout_max_rate = 900000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	.flags = PLL_HAS_POSTDIV | PLL_POSTDIV_FIXED_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }