^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PLL clock descriptions for TI DA850/OMAP-L138/AM18XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/da8xx-cfgchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OCSEL_OCSRC_OSCIN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OCSEL_OCSRC_PLL0_SYSCLK(n) (0x16 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OCSEL_OCSRC_PLL1_OBSCLK 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OCSEL_OCSRC_PLL1_SYSCLK(n) (0x16 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const struct davinci_pll_clk_info da850_pll0_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .name = "pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .unlock_reg = CFGCHIP(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .unlock_mask = CFGCHIP0_PLL_MASTER_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .pllm_mask = GENMASK(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .pllm_min = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .pllm_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .pllout_min_rate = 300000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .pllout_max_rate = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PLL_HAS_EXTCLKSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * meaning that we could change the divider as long as we keep the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * ratio between all of the clocks, but we don't support that because there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * currently not a need for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const char * const da850_pll0_obsclk_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "oscin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "pll0_sysclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "pll0_sysclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "pll0_sysclk3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "pll0_sysclk4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "pll0_sysclk5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "pll0_sysclk6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "pll0_sysclk7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "pll1_obsclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static u32 da850_pll0_obsclk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) OCSEL_OCSRC_OSCIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) OCSEL_OCSRC_PLL0_SYSCLK(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) OCSEL_OCSRC_PLL0_SYSCLK(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) OCSEL_OCSRC_PLL0_SYSCLK(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) OCSEL_OCSRC_PLL0_SYSCLK(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) OCSEL_OCSRC_PLL0_SYSCLK(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) OCSEL_OCSRC_PLL0_SYSCLK(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) OCSEL_OCSRC_PLL0_SYSCLK(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) OCSEL_OCSRC_PLL1_OBSCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "pll0_obsclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .parent_names = da850_pll0_obsclk_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .num_parents = ARRAY_SIZE(da850_pll0_obsclk_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .table = da850_pll0_obsclk_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .ocsrc_mask = GENMASK(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clk_register_clkdev(clk, "pll0_sysclk2", "da850-async3-clksrc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk_register_clkdev(clk, "pll0_sysclk3", "da850-async1-clksrc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk_register_clkdev(clk, "pll0_sysclk6", "da850-psc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk = clk_register_fixed_factor(dev, "async2", "pll0_auxclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CLK_IS_CRITICAL, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk_register_clkdev(clk, NULL, "i2c_davinci.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk_register_clkdev(clk, "timer0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clk_register_clkdev(clk, NULL, "davinci-wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) davinci_pll_obsclk_register(dev, &da850_pll0_obsclk_info, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) &pll0_sysclk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) &pll0_sysclk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) &pll0_sysclk3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) &pll0_sysclk4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) &pll0_sysclk5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &pll0_sysclk6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) &pll0_sysclk7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void of_da850_pll0_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct regmap *cfgchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pr_err("%s: ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) of_davinci_pll_init(NULL, node, &da850_pll0_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) &da850_pll0_obsclk_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) da850_pll0_sysclk_info, 7, base, cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct davinci_pll_clk_info da850_pll1_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .name = "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .unlock_reg = CFGCHIP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .unlock_mask = CFGCHIP3_PLL1_MASTER_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .pllm_mask = GENMASK(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .pllm_min = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .pllm_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .pllout_min_rate = 300000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .pllout_max_rate = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .flags = PLL_HAS_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const char * const da850_pll1_obsclk_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "oscin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "pll1_sysclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "pll1_sysclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "pll1_sysclk3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static u32 da850_pll1_obsclk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) OCSEL_OCSRC_OSCIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) OCSEL_OCSRC_PLL1_SYSCLK(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) OCSEL_OCSRC_PLL1_SYSCLK(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) OCSEL_OCSRC_PLL1_SYSCLK(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .name = "pll1_obsclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .parent_names = da850_pll1_obsclk_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .num_parents = ARRAY_SIZE(da850_pll1_obsclk_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .table = da850_pll1_obsclk_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .ocsrc_mask = GENMASK(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk_register_clkdev(clk, "pll1_sysclk2", "da850-async3-clksrc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) davinci_pll_obsclk_register(dev, &da850_pll1_obsclk_info, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) &pll1_sysclk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) &pll1_sysclk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) &pll1_sysclk3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) &da850_pll1_obsclk_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) da850_pll1_sysclk_info, 3, base, cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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