Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const struct davinci_pll_clk_info da830_pll_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.name = "pll0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	.pllm_mask = GENMASK(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	.pllm_min = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	.pllm_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.pllout_min_rate = 300000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.pllout_max_rate = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * meaning that we could change the divider as long as we keep the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * ratio between all of the clocks, but we don't support that because there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * currently not a need for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	clk_register_clkdev(clk, NULL, "i2c_davinci.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	clk_register_clkdev(clk, "timer0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	clk_register_clkdev(clk, NULL, "davinci-wdt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }