^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/da8xx-cfgchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_data/clk-da8xx-cfgchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* --- Gate clocks --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DA8XX_GATE_CLOCK_IS_DIV4P5 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct da8xx_cfgchip_gate_clk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 cfgchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct da8xx_cfgchip_gate_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define to_da8xx_cfgchip_gate_clk(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) container_of((_hw), struct da8xx_cfgchip_gate_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int da8xx_cfgchip_gate_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void da8xx_cfgchip_gate_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int da8xx_cfgchip_gate_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) regmap_read(clk->regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return !!(val & clk->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static unsigned long da8xx_cfgchip_div4p5_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* this clock divides by 4.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return parent_rate * 2 / 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct clk_ops da8xx_cfgchip_gate_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .enable = da8xx_cfgchip_gate_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .disable = da8xx_cfgchip_gate_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct clk_ops da8xx_cfgchip_div4p5_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .enable = da8xx_cfgchip_gate_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .disable = da8xx_cfgchip_gate_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .recalc_rate = da8xx_cfgchip_div4p5_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct da8xx_cfgchip_gate_clk * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) da8xx_cfgchip_gate_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const struct da8xx_cfgchip_gate_clk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct da8xx_cfgchip_gate_clk *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) parent = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ERR_CAST(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) parent_name = __clk_get_name(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) init.name = info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) init.ops = &da8xx_cfgchip_div4p5_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) init.ops = &da8xx_cfgchip_gate_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) gate->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) gate->reg = info->cfgchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) gate->mask = info->bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = devm_clk_hw_register(dev, &gate->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "ehrpwm_tbclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .cfgchip = CFGCHIP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .bit = CFGCHIP1_TBCLKSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int __init da8xx_cfgchip_register_tbclk(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct da8xx_cfgchip_gate_clk *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (IS_ERR(gate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return PTR_ERR(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct da8xx_cfgchip_gate_clk_info da8xx_div4p5ena_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = "div4.5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .cfgchip = CFGCHIP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .bit = CFGCHIP3_DIV45PENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .flags = DA8XX_GATE_CLOCK_IS_DIV4P5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int __init da8xx_cfgchip_register_div4p5(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct da8xx_cfgchip_gate_clk *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return PTR_ERR_OR_ZERO(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) of_da8xx_cfgchip_gate_clk_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const struct da8xx_cfgchip_gate_clk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct da8xx_cfgchip_gate_clk *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) gate = da8xx_cfgchip_gate_clk_register(dev, info, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (IS_ERR(gate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return PTR_ERR(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int __init of_da8xx_tbclksync_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_tbclksync_info, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int __init of_da8xx_div4p5ena_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_div4p5ena_info, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* --- MUX clocks --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct da8xx_cfgchip_mux_clk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) const char *parent0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const char *parent1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 cfgchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct da8xx_cfgchip_mux_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define to_da8xx_cfgchip_mux_clk(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) container_of((_hw), struct da8xx_cfgchip_mux_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int val = index ? clk->mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) regmap_read(clk->regmap, clk->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return (val & clk->mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct clk_ops da8xx_cfgchip_mux_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .set_parent = da8xx_cfgchip_mux_clk_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .get_parent = da8xx_cfgchip_mux_clk_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct da8xx_cfgchip_mux_clk * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) da8xx_cfgchip_mux_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const struct da8xx_cfgchip_mux_clk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) const char * const parent_names[] = { info->parent0, info->parent1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct da8xx_cfgchip_mux_clk *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) init.name = info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) init.ops = &da8xx_cfgchip_mux_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) init.num_parents = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mux->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mux->reg = info->cfgchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mux->mask = info->bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = devm_clk_hw_register(dev, &mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct da8xx_cfgchip_mux_clk_info da850_async1_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .name = "async1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .parent0 = "pll0_sysclk3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .parent1 = "div4.5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .cfgchip = CFGCHIP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .bit = CFGCHIP3_EMA_CLKSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int __init da8xx_cfgchip_register_async1(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct da8xx_cfgchip_mux_clk *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (IS_ERR(mux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return PTR_ERR(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct da8xx_cfgchip_mux_clk_info da850_async3_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .name = "async3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .parent0 = "pll0_sysclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .parent1 = "pll1_sysclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .cfgchip = CFGCHIP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .bit = CFGCHIP3_ASYNC3_CLKSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int __init da850_cfgchip_register_async3(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct da8xx_cfgchip_mux_clk *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct clk_hw *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (IS_ERR(mux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return PTR_ERR(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) parent = clk_hw_get_parent_by_index(&mux->hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) clk_set_parent(mux->hw.clk, parent->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_warn(dev, "Failed to find async3 parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) of_da8xx_cfgchip_init_mux_clock(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) const struct da8xx_cfgchip_mux_clk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct da8xx_cfgchip_mux_clk *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (IS_ERR(mux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return PTR_ERR(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int __init of_da850_async1_init(struct device *dev, struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async1_info, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* --- USB 2.0 PHY clock --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct da8xx_usb0_clk48 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct clk *fck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define to_da8xx_usb0_clk48(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) container_of((_hw), struct da8xx_usb0_clk48, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int da8xx_usb0_clk48_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* The USB 2.0 PSC clock is only needed temporarily during the USB 2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * PHY clock enable, but since clk_prepare() can't be called in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * atomic context (i.e. in clk_enable()), we have to prepare it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return clk_prepare(usb0->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void da8xx_usb0_clk48_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clk_unprepare(usb0->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int da8xx_usb0_clk48_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * temporaily. It can be turned back off once the PLL is locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) clk_enable(usb0->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) val = CFGCHIP2_PHY_PLLON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) val & CFGCHIP2_PHYCLKGD, 0, 500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) clk_disable(usb0->fck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void da8xx_usb0_clk48_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) val = CFGCHIP2_PHYPWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int da8xx_usb0_clk48_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regmap_read(usb0->regmap, CFGCHIP(2), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return !!(val & CFGCHIP2_PHYCLKGD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* The parent clock rate must be one of the following */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mask = CFGCHIP2_REFFREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) switch (parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) val = CFGCHIP2_REFFREQ_12MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case 13000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) val = CFGCHIP2_REFFREQ_13MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) val = CFGCHIP2_REFFREQ_19_2MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case 20000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) val = CFGCHIP2_REFFREQ_20MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case 24000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) val = CFGCHIP2_REFFREQ_24MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) val = CFGCHIP2_REFFREQ_26MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case 38400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) val = CFGCHIP2_REFFREQ_38_4MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case 40000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) val = CFGCHIP2_REFFREQ_40MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case 48000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) val = CFGCHIP2_REFFREQ_48MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* USB 2.0 PLL always supplies 48MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 48000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static long da8xx_usb0_clk48_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 48000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int da8xx_usb0_clk48_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return regmap_write_bits(usb0->regmap, CFGCHIP(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CFGCHIP2_USB2PHYCLKMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) index ? CFGCHIP2_USB2PHYCLKMUX : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static u8 da8xx_usb0_clk48_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) regmap_read(usb0->regmap, CFGCHIP(2), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return (val & CFGCHIP2_USB2PHYCLKMUX) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct clk_ops da8xx_usb0_clk48_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .prepare = da8xx_usb0_clk48_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .unprepare = da8xx_usb0_clk48_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .enable = da8xx_usb0_clk48_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .disable = da8xx_usb0_clk48_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .is_enabled = da8xx_usb0_clk48_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .recalc_rate = da8xx_usb0_clk48_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .round_rate = da8xx_usb0_clk48_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .set_parent = da8xx_usb0_clk48_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .get_parent = da8xx_usb0_clk48_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static struct da8xx_usb0_clk48 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) da8xx_cfgchip_register_usb0_clk48(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct clk *fck_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct da8xx_usb0_clk48 *usb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) fck_clk = devm_clk_get(dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (IS_ERR(fck_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (PTR_ERR(fck_clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(dev, "Missing fck clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return ERR_CAST(fck_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) usb0 = devm_kzalloc(dev, sizeof(*usb0), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!usb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) init.name = "usb0_clk48";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) init.ops = &da8xx_usb0_clk48_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) init.num_parents = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) usb0->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) usb0->fck = fck_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) usb0->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = devm_clk_hw_register(dev, &usb0->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return usb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* --- USB 1.1 PHY clock --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct da8xx_usb1_clk48 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define to_da8xx_usb1_clk48(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) container_of((_hw), struct da8xx_usb1_clk48, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int da8xx_usb1_clk48_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return regmap_write_bits(usb1->regmap, CFGCHIP(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) CFGCHIP2_USB1PHYCLKMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) index ? CFGCHIP2_USB1PHYCLKMUX : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static u8 da8xx_usb1_clk48_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) regmap_read(usb1->regmap, CFGCHIP(2), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return (val & CFGCHIP2_USB1PHYCLKMUX) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct clk_ops da8xx_usb1_clk48_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .set_parent = da8xx_usb1_clk48_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .get_parent = da8xx_usb1_clk48_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * da8xx_cfgchip_register_usb1_clk48 - Register a new USB 1.1 PHY clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * @dev: The device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * @regmap: The CFGCHIP regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static struct da8xx_usb1_clk48 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) da8xx_cfgchip_register_usb1_clk48(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) const char * const parent_names[] = { "usb0_clk48", "usb_refclkin" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct da8xx_usb1_clk48 *usb1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) usb1 = devm_kzalloc(dev, sizeof(*usb1), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!usb1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) init.name = "usb1_clk48";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) init.ops = &da8xx_usb1_clk48_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) init.num_parents = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) usb1->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) usb1->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = devm_clk_hw_register(dev, &usb1->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return usb1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int da8xx_cfgchip_register_usb_phy_clk(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct da8xx_usb0_clk48 *usb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct da8xx_usb1_clk48 *usb1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct clk_hw *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (IS_ERR(usb0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return PTR_ERR(usb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * All existing boards use pll0_auxclk as the parent and new boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * should use device tree, so hard-coding the value (1) here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) parent = clk_hw_get_parent_by_index(&usb0->hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) clk_set_parent(usb0->hw.clk, parent->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_warn(dev, "Failed to find usb0 parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (IS_ERR(usb1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return PTR_ERR(usb1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * All existing boards use usb0_clk48 as the parent and new boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * should use device tree, so hard-coding the value (0) here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) parent = clk_hw_get_parent_by_index(&usb1->hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) clk_set_parent(usb1->hw.clk, parent->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_warn(dev, "Failed to find usb1 parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) clk_hw_register_clkdev(&usb0->hw, "usb0_clk48", "da8xx-usb-phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) clk_hw_register_clkdev(&usb1->hw, "usb1_clk48", "da8xx-usb-phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int of_da8xx_usb_phy_clk_init(struct device *dev, struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct da8xx_usb0_clk48 *usb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct da8xx_usb1_clk48 *usb1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) clk_data->num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (IS_ERR(usb0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (PTR_ERR(usb0) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_warn(dev, "Failed to register usb0_clk48 (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PTR_ERR(usb0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) clk_data->hws[0] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) clk_data->hws[0] = &usb0->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (IS_ERR(usb1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (PTR_ERR(usb1) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_warn(dev, "Failed to register usb1_clk48 (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PTR_ERR(usb1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) clk_data->hws[1] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) clk_data->hws[1] = &usb1->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* --- platform device --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const struct of_device_id da8xx_cfgchip_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .compatible = "ti,da830-tbclksync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .data = of_da8xx_tbclksync_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .compatible = "ti,da830-div4p5ena",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .data = of_da8xx_div4p5ena_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .compatible = "ti,da850-async1-clksrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .data = of_da850_async1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .compatible = "ti,da850-async3-clksrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .data = of_da850_async3_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .compatible = "ti,da830-usb-phy-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .data = of_da8xx_usb_phy_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const struct platform_device_id da8xx_cfgchip_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .name = "da830-tbclksync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_tbclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .name = "da830-div4p5ena",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_div4p5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .name = "da850-async1-clksrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_async1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .name = "da850-async3-clksrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .driver_data = (kernel_ulong_t)da850_cfgchip_register_async3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .name = "da830-usb-phy-clks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_usb_phy_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) typedef int (*da8xx_cfgchip_init)(struct device *dev, struct regmap *regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int da8xx_cfgchip_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) da8xx_cfgchip_init clk_init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct regmap *regmap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) of_id = of_match_device(da8xx_cfgchip_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) clk_init = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) parent = of_get_parent(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) regmap = syscon_node_to_regmap(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } else if (pdev->id_entry && pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) clk_init = (void *)pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) regmap = pdata->cfgchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (!clk_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_err(dev, "unable to find driver data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (IS_ERR_OR_NULL(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_err(dev, "no regmap for CFGCHIP syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return regmap ? PTR_ERR(regmap) : -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return clk_init(dev, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static struct platform_driver da8xx_cfgchip_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .probe = da8xx_cfgchip_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .name = "da8xx-cfgchip-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .of_match_table = da8xx_cfgchip_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .id_table = da8xx_cfgchip_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int __init da8xx_cfgchip_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return platform_driver_register(&da8xx_cfgchip_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* has to be postcore_initcall because PSC devices depend on the async3 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) postcore_initcall(da8xx_cfgchip_driver_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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