^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Clock implementation for VIA/Wondermedia SoC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LEGACY_PMC_BASE 0xD8130000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* All clocks share the same lock as none can be changed concurrently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static DEFINE_SPINLOCK(_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct clk_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void __iomem *div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void __iomem *en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int en_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Add new PLL_TYPE_x definitions here as required. Use the first known model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * to support the new type as the name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLL_TYPE_VT8500 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLL_TYPE_WM8650 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PLL_TYPE_WM8750 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PLL_TYPE_WM8850 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clk_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void __iomem *pmc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static __init void vtwm_set_pmc_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct device_node *np =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pmc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pr_err("%s:of_iomap(pmc) failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VT8500_PMC_BUSY_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void vt8500_pmc_wait_busy(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int vt8500_dclk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk_device *cdev = to_clk_device(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 en_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) spin_lock_irqsave(cdev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) en_val = readl(cdev->en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) en_val |= BIT(cdev->en_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel(en_val, cdev->en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) spin_unlock_irqrestore(cdev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void vt8500_dclk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk_device *cdev = to_clk_device(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 en_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spin_lock_irqsave(cdev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) en_val = readl(cdev->en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) en_val &= ~BIT(cdev->en_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(en_val, cdev->en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spin_unlock_irqrestore(cdev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int vt8500_dclk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk_device *cdev = to_clk_device(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return en_val ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk_device *cdev = to_clk_device(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 div = readl(cdev->div_reg) & cdev->div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Special case for SDMMC devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) div = 64 * (div & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* div == 0 is actually the highest divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (div == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) div = (cdev->div_mask + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct clk_device *cdev = to_clk_device(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) divisor = *prate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* If prate / rate would be decimal, incr the divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (rate * divisor < *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) divisor++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * If this is a request for SDMMC we have to adjust the divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * when >31 to use the fixed predivisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) divisor = 64 * ((divisor / 64) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return *prate / divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct clk_device *cdev = to_clk_device(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) divisor = parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (divisor == cdev->div_mask + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) divisor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* SDMMC mask may need to be corrected before testing if its valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Bit 5 is a fixed /64 predivisor. If the requested divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * is >31 then correct for the fixed divisor being required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) divisor = 0x20 + (divisor / 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (divisor > cdev->div_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pr_err("%s: invalid divisor for clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spin_lock_irqsave(cdev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) vt8500_pmc_wait_busy();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(divisor, cdev->div_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) vt8500_pmc_wait_busy();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) spin_unlock_irqrestore(cdev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct clk_ops vt8500_gated_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .enable = vt8500_dclk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .disable = vt8500_dclk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .is_enabled = vt8500_dclk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct clk_ops vt8500_divisor_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .round_rate = vt8500_dclk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .set_rate = vt8500_dclk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .recalc_rate = vt8500_dclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct clk_ops vt8500_gated_divisor_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .enable = vt8500_dclk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .disable = vt8500_dclk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .is_enabled = vt8500_dclk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .round_rate = vt8500_dclk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .set_rate = vt8500_dclk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .recalc_rate = vt8500_dclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_INIT_GATED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_INIT_DIVISOR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static __init void vtwm_device_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 en_reg, div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct clk_device *dev_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int clk_init_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) vtwm_set_pmc_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (WARN_ON(!dev_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_clk->lock = &_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) rc = of_property_read_u32(node, "enable-reg", &en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_clk->en_reg = pmc_base + en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pr_err("%s: enable-bit property required for gated clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk_init_flags |= CLK_INIT_GATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) rc = of_property_read_u32(node, "divisor-reg", &div_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_clk->div_reg = pmc_base + div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * use 0x1f as the default mask since it covers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * almost all the clocks and reduces dts properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_clk->div_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk_init_flags |= CLK_INIT_DIVISOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) switch (clk_init_flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case CLK_INIT_GATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) init.ops = &vt8500_gated_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case CLK_INIT_DIVISOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) init.ops = &vt8500_divisor_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case CLK_INIT_GATED_DIVISOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) init.ops = &vt8500_gated_divisor_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pr_err("%s: Invalid clock description in device tree\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) kfree(dev_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) hw = &dev_clk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rc = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (WARN_ON(rc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) kfree(dev_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) clk_hw_register_clkdev(hw, clk_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* PLL clock related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Helper macros for PLL_VT8500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define VT8500_BITS_TO_FREQ(r, m, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ((r / d) * m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define VT8500_BITS_TO_VAL(m, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Helper macros for PLL_WM8650 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define WM8650_PLL_MUL(x) (x & 0x3FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) (r * m / (d1 * (1 << d2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define WM8650_BITS_TO_VAL(m, d1, d2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Helper macros for PLL_WM8750 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define WM8750_BITS_TO_FREQ(r, m, d1, d2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (r * (m+1) / ((d1+1) * (1 << d2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define WM8750_BITS_TO_VAL(f, m, d1, d2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Helper macros for PLL_WM8850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define WM8850_PLL_MUL(x) ((((x >> 16) & 0x7F) + 1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define WM8850_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define WM8850_BITS_TO_FREQ(r, m, d1, d2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define WM8850_BITS_TO_VAL(m, d1, d2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 *multiplier, u32 *prediv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pr_err("%s: requested rate out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *multiplier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *prediv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (rate <= parent_rate * 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* use the prediv to double the resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *prediv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *prediv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *multiplier = rate / (parent_rate / *prediv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) tclk = (parent_rate / *prediv) * *multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (tclk != rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rate, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * M * parent [O1] => / P [O2] => / D [O3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Where O1 is 900MHz...3GHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * O2 is 600MHz >= (M * parent) / P >= 300MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * Possible ranges (O3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * D = 8: 37,5MHz...75MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * D = 4: 75MHz...150MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * D = 2: 150MHz...300MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * D = 1: 300MHz...600MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int wm8650_find_pll_bits(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned long parent_rate, u32 *multiplier, u32 *divisor1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 *divisor2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned long O1, min_err, rate_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!parent_rate || (rate < 37500000) || (rate > 600000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) *divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) rate <= 300000000 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Divisor P cannot be calculated. Test all divisors and find where M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * will be as close as possible to the requested rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) min_err = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) O1 = rate * *divisor1 * (1 << (*divisor2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rate_err = O1 % parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (rate_err < min_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *multiplier = O1 / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (rate_err == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) min_err = rate_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if ((*multiplier < 3) || (*multiplier > 1023))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pr_warn("%s: rate error is %lu\n", __func__, min_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* calculate frequency (MHz) after pre-divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if ((freq < 10) || (freq > 200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (freq >= 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) else if (freq >= 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) else if (freq >= 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) else if (freq >= 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) else if (freq >= 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) else if (freq >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else if (freq >= 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int div1, div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned long tclk, rate_err, best_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) best_err = (unsigned long)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Find the closest match (lower or equal to requested) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (div1 = 1; div1 >= 0; div1--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) for (div2 = 7; div2 >= 0; div2--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (mul = 0; mul <= 255; mul++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (tclk > rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* error will always be +ve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) rate_err = rate - tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (rate_err == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *filter = wm8750_get_filter(parent_rate, div1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *multiplier = mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) *divisor1 = div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) *divisor2 = div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (rate_err < best_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) best_err = rate_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *multiplier = mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *divisor1 = div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *divisor2 = div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (best_err == (unsigned long)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pr_warn("%s: impossible rate %lu\n", __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* if we got here, it wasn't an exact match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rate - best_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) *filter = wm8750_get_filter(parent_rate, *divisor1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 *multiplier, u32 *divisor1, u32 *divisor2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int div1, div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned long tclk, rate_err, best_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) best_err = (unsigned long)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Find the closest match (lower or equal to requested) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) for (div1 = 1; div1 >= 0; div1--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) for (div2 = 3; div2 >= 0; div2--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) for (mul = 0; mul <= 127; mul++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) tclk = parent_rate * ((mul + 1) * 2) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ((div1 + 1) * (1 << div2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (tclk > rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* error will always be +ve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rate_err = rate - tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (rate_err == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *multiplier = mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) *divisor1 = div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) *divisor2 = div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (rate_err < best_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) best_err = rate_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) *multiplier = mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) *divisor1 = div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) *divisor2 = div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (best_err == (unsigned long)-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pr_warn("%s: impossible rate %lu\n", __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* if we got here, it wasn't an exact match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) rate - best_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 filter, mul, div1, div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 pll_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) switch (pll->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case PLL_TYPE_VT8500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pll_val = VT8500_BITS_TO_VAL(mul, div1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case PLL_TYPE_WM8650:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case PLL_TYPE_WM8750:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case PLL_TYPE_WM8850:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pr_err("%s: invalid pll type\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) vt8500_pmc_wait_busy();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) writel(pll_val, pll->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) vt8500_pmc_wait_busy();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 filter, mul, div1, div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) long round_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) switch (pll->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case PLL_TYPE_VT8500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case PLL_TYPE_WM8650:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case PLL_TYPE_WM8750:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case PLL_TYPE_WM8850:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return round_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 pll_val = readl(pll->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned long pll_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) switch (pll->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case PLL_TYPE_VT8500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pll_freq /= VT8500_PLL_DIV(pll_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case PLL_TYPE_WM8650:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) pll_freq /= WM8650_PLL_DIV(pll_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case PLL_TYPE_WM8750:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pll_freq /= WM8750_PLL_DIV(pll_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case PLL_TYPE_WM8850:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pll_freq /= WM8850_PLL_DIV(pll_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) pll_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return pll_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const struct clk_ops vtwm_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .round_rate = vtwm_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .set_rate = vtwm_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .recalc_rate = vtwm_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct clk_pll *pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) vtwm_set_pmc_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) rc = of_property_read_u32(node, "reg", ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (WARN_ON(rc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (WARN_ON(!pll_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) pll_clk->reg = pmc_base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pll_clk->lock = &_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) pll_clk->type = pll_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) init.ops = &vtwm_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pll_clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) hw = &pll_clk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) rc = clk_hw_register(NULL, &pll_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (WARN_ON(rc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) kfree(pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) clk_hw_register_clkdev(hw, clk_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Wrappers for initialization functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static void __init vt8500_pll_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static void __init wm8650_pll_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static void __init wm8750_pll_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static void __init wm8850_pll_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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