^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for IDT Versaclock 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Possible optimizations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - Use spread spectrum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - Use integer divider in FOD if applicable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rational.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <dt-bindings/clk/versaclock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* VersaClock5 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VC5_OTP_CONTROL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Factory-reserved register block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VC5_RSVD_DEVICE_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VC5_RSVD_ADC_GAIN_7_0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VC5_RSVD_ADC_GAIN_15_8 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VC5_RSVD_ADC_OFFSET_7_0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VC5_RSVD_ADC_OFFSET_15_8 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VC5_RSVD_TEMPY 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VC5_RSVD_OFFSET_TBIN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VC5_RSVD_GAIN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VC5_RSVD_TEST_NP 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VC5_RSVD_UNUSED 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VC5_RSVD_CLK_AMP_123 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Configuration register block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VC5_PRIM_SRC_SHDN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VC5_PRIM_SRC_SHDN_SP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VC5_VCO_BAND 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VC5_XTAL_X1_LOAD_CAP 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VC5_XTAL_X2_LOAD_CAP 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VC5_REF_DIVIDER 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VC5_VCO_CTRL_AND_PREDIV 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VC5_FEEDBACK_INT_DIV 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VC5_FEEDBACK_INT_DIV_BITS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VC5_RC_CONTROL0 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VC5_RC_CONTROL1 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* These registers are named "Unused Factory Reserved Registers" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Output divider control for divider 1,2,3,4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VC5_OUT_DIV_CONTROL_RESET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Clock control register for clock 1,2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VC5_CLK_OE_SHDN 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VC5_CLK_OS_SHDN 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VC5_GLOBAL_REGISTER 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VC5_PLL_VCO_MIN 2500000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VC5_PLL_VCO_MAX 3000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* VC5 Input mux settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VC5_MUX_IN_XIN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VC5_MUX_IN_CLKIN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Maximum number of clk_out supported by this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VC5_MAX_CLK_OUT_NUM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Maximum number of FODs supported by this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VC5_MAX_FOD_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* flags to describe chip features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* chip has built-in oscilator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VC5_HAS_INTERNAL_XTAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* chip has PFD requency doubler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VC5_HAS_PFD_FREQ_DBL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* chip has bits to disable FOD sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VC5_HAS_BYPASS_SYNC_BIT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Supported IDT VC5 models. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum vc5_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) IDT_VC5_5P49V5923,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) IDT_VC5_5P49V5925,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) IDT_VC5_5P49V5933,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) IDT_VC5_5P49V5935,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) IDT_VC6_5P49V6901,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) IDT_VC6_5P49V6965,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Structure to describe features of a particular VC5 model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct vc5_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const enum vc5_model model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const unsigned int clk_fod_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const unsigned int clk_out_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct vc5_driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct vc5_hw_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct vc5_driver_data *vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 div_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 div_frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct vc5_out_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct vc5_driver_data *vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int clk_output_cfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int clk_output_cfg0_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct vc5_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct vc5_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk *pin_xin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct clk *pin_clkin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned char clk_mux_ins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct clk_hw clk_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct clk_hw clk_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct clk_hw clk_pfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct vc5_hw_data clk_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * VersaClock5 i2c regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Factory reserved regs, make them read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (reg <= 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Factory reserved regs, make them read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct regmap_config vc5_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .max_register = 0x76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .writeable_reg = vc5_regmap_is_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * VersaClock5 input multiplexer between XTAL and CLKIN divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct vc5_driver_data *vc5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) container_of(hw, struct vc5_driver_data, clk_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) src &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_warn(&vc5->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "Invalid clock input configuration (%02x)\n", src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct vc5_driver_data *vc5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) container_of(hw, struct vc5_driver_data, clk_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if ((index > 1) || !vc5->clk_mux_ins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) src = VC5_PRIM_SRC_SHDN_EN_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (index == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) src = VC5_PRIM_SRC_SHDN_EN_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else /* Invalid; should have been caught by vc5_probe() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct clk_ops vc5_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .set_parent = vc5_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .get_parent = vc5_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct vc5_driver_data *vc5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) container_of(hw, struct vc5_driver_data, clk_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int premul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) parent_rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct vc5_driver_data *vc5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) container_of(hw, struct vc5_driver_data, clk_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if ((parent_rate * 2) == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct clk_ops vc5_dbl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .recalc_rate = vc5_dbl_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .round_rate = vc5_dbl_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .set_rate = vc5_dbl_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct vc5_driver_data *vc5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) container_of(hw, struct vc5_driver_data, clk_pfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int prediv, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* The bypass_prediv is set, PLL fed from Ref_in directly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long idiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* PLL cannot operate with input clock above 50 MHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (rate > 50000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* CLKIN within range of PLL input, feed directly to PLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (*parent_rate <= 50000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) idiv = DIV_ROUND_UP(*parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (idiv > 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return *parent_rate / idiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct vc5_driver_data *vc5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) container_of(hw, struct vc5_driver_data, clk_pfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long idiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* CLKIN within range of PLL input, feed directly to PLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (parent_rate <= 50000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) idiv = DIV_ROUND_UP(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* We have dedicated div-2 predivider. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (idiv == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) div = VC5_REF_DIVIDER_SEL_PREDIV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) div = VC5_REF_DIVIDER_REF_DIV(idiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct clk_ops vc5_pfd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .recalc_rate = vc5_pfd_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .round_rate = vc5_pfd_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .set_rate = vc5_pfd_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * VersaClock5 PLL/VCO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct vc5_driver_data *vc5 = hwdata->vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 div_int, div_frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 fb[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) div_int = (fb[0] << 4) | (fb[1] >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* The PLL divider has 12 integer bits and 24 fractional bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 div_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u64 div_frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (rate < VC5_PLL_VCO_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) rate = VC5_PLL_VCO_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (rate > VC5_PLL_VCO_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rate = VC5_PLL_VCO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Determine integer part, which is 12 bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) div_int = rate / *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (div_int > 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) rate = *parent_rate * 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Determine best fractional part, which is 24 bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) div_frc = rate % *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) div_frc *= BIT(24) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) do_div(div_frc, *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) hwdata->div_int = div_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) hwdata->div_frc = (u32)div_frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct vc5_driver_data *vc5 = hwdata->vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u8 fb[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) fb[0] = hwdata->div_int >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fb[1] = hwdata->div_int << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fb[2] = hwdata->div_frc >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) fb[3] = hwdata->div_frc >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) fb[4] = hwdata->div_frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct clk_ops vc5_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .recalc_rate = vc5_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .round_rate = vc5_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .set_rate = vc5_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct vc5_driver_data *vc5 = hwdata->vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* VCO frequency is divided by two before entering FOD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 f_in = parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 div_int, div_frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 od_int[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u8 od_frc[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) od_int, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) od_frc, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) div_int = (od_int[0] << 4) | (od_int[1] >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) (od_frc[2] << 6) | (od_frc[3] >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Avoid division by zero if the output is not configured. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (div_int == 0 && div_frc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* The PLL divider has 12 integer bits and 30 fractional bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* VCO frequency is divided by two before entering FOD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 f_in = *parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 div_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u64 div_frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Determine integer part, which is 12 bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) div_int = f_in / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * WARNING: The clock chip does not output signal if the integer part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * of the divider is 0xfff and fractional part is non-zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * Clamp the divider at 0xffe to keep the code simple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (div_int > 0xffe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) div_int = 0xffe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) rate = f_in / div_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Determine best fractional part, which is 30 bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) div_frc = f_in % rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) div_frc <<= 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) do_div(div_frc, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) hwdata->div_int = div_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hwdata->div_frc = (u32)div_frc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct vc5_driver_data *vc5 = hwdata->vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u8 data[14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hwdata->div_frc >> 22, hwdata->div_frc >> 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hwdata->div_frc >> 6, hwdata->div_frc << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) hwdata->div_int >> 4, hwdata->div_int << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) data, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * Toggle magic bit in undocumented register for unknown reason.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * This is what the IDT timing commander tool does and the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * datasheet somewhat implies this is needed, but the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * and the bit is not documented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) VC5_GLOBAL_REGISTER_GLOBAL_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) VC5_GLOBAL_REGISTER_GLOBAL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const struct clk_ops vc5_fod_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .recalc_rate = vc5_fod_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .round_rate = vc5_fod_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .set_rate = vc5_fod_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int vc5_clk_out_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct vc5_driver_data *vc5 = hwdata->vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) VC5_OUT_DIV_CONTROL_SEL_EXT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) VC5_OUT_DIV_CONTROL_EN_FOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned int src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * When enabling a FOD, all currently enabled FODs are briefly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * stopped in order to synchronize all of them. This causes a clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * disruption to any unrelated chips that might be already using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * other clock outputs. Bypass the sync feature to avoid the issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * which is possible on the VersaClock 6E family via reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = regmap_update_bits(vc5->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) VC5_RESERVED_X0(hwdata->num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) VC5_RESERVED_X0_BYPASS_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) VC5_RESERVED_X0_BYPASS_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * If the input mux is disabled, enable it first and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * select source from matching FOD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if ((src & mask) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = regmap_update_bits(vc5->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) VC5_OUT_DIV_CONTROL(hwdata->num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mask | VC5_OUT_DIV_CONTROL_RESET, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Enable the clock buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) VC5_CLK_OUTPUT_CFG1_EN_CLKBUF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (hwdata->clk_output_cfg0_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hwdata->num, hwdata->clk_output_cfg0_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) hwdata->clk_output_cfg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) regmap_update_bits(vc5->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) hwdata->clk_output_cfg0_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) hwdata->clk_output_cfg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static void vc5_clk_out_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct vc5_driver_data *vc5 = hwdata->vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Disable the clock buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct vc5_driver_data *vc5 = hwdata->vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) VC5_OUT_DIV_CONTROL_SEL_EXT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) VC5_OUT_DIV_CONTROL_EN_FOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) VC5_OUT_DIV_CONTROL_EN_FOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) VC5_OUT_DIV_CONTROL_SEL_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned int src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) src &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (src == 0) /* Input mux set to DISABLED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (src == extclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev_warn(&vc5->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "Invalid clock output configuration (%02x)\n", src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct vc5_driver_data *vc5 = hwdata->vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) VC5_OUT_DIV_CONTROL_SELB_NORM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) VC5_OUT_DIV_CONTROL_SEL_EXT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) VC5_OUT_DIV_CONTROL_EN_FOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) VC5_OUT_DIV_CONTROL_SEL_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u8 src = VC5_OUT_DIV_CONTROL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) src |= VC5_OUT_DIV_CONTROL_EN_FOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) src |= extclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) mask, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct clk_ops vc5_clk_out_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .prepare = vc5_clk_out_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .unprepare = vc5_clk_out_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .set_parent = vc5_clk_out_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .get_parent = vc5_clk_out_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct vc5_driver_data *vc5 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (idx >= vc5->chip_info->clk_out_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return &vc5->clk_out[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int vc5_map_index_to_output(const enum vc5_model model,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) const unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) switch (model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case IDT_VC5_5P49V5933:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return (n == 0) ? 0 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case IDT_VC5_5P49V5923:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case IDT_VC5_5P49V5925:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case IDT_VC5_5P49V5935:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case IDT_VC6_5P49V6901:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case IDT_VC6_5P49V6965:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int vc5_update_mode(struct device_node *np_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct vc5_out_data *clk_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!of_property_read_u32(np_output, "idt,mode", &value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case VC5_CLK_OUTPUT_CFG0_CFG_CMOS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) case VC5_CLK_OUTPUT_CFG0_CFG_LVDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) clk_out->clk_output_cfg0 |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int vc5_update_power(struct device_node *np_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct vc5_out_data *clk_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!of_property_read_u32(np_output, "idt,voltage-microvolt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) &value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case 1800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case 2500000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case 3300000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int vc5_update_slew(struct device_node *np_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct vc5_out_data *clk_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case 80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case 85:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case 100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) clk_out->clk_output_cfg0 |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) VC5_CLK_OUTPUT_CFG0_SLEW_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int vc5_get_output_config(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct vc5_out_data *clk_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct device_node *np_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) char *child_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (!child_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) np_output = of_get_child_by_name(client->dev.of_node, child_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) kfree(child_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!np_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ret = vc5_update_mode(np_output, clk_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) goto output_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ret = vc5_update_power(np_output, clk_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) goto output_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = vc5_update_slew(np_output, clk_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) output_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "Invalid clock output configuration OUT%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) clk_out->num + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) of_node_put(np_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct of_device_id clk_vc5_of_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct vc5_driver_data *vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) const char *parent_names[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) unsigned int n, idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (!vc5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) i2c_set_clientdata(client, vc5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) vc5->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) vc5->chip_info = of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) vc5->pin_xin = devm_clk_get(&client->dev, "xin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (IS_ERR(vc5->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_err(&client->dev, "failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return PTR_ERR(vc5->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* Register clock input mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!IS_ERR(vc5->pin_xin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) vc5->pin_xin = clk_register_fixed_rate(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "internal-xtal", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) 0, 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (IS_ERR(vc5->pin_xin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return PTR_ERR(vc5->pin_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!IS_ERR(vc5->pin_clkin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) parent_names[init.num_parents++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) __clk_get_name(vc5->pin_clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (!init.num_parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dev_err(&client->dev, "no input clock specified!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) init.ops = &vc5_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) vc5->clk_mux.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Register frequency doubler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) init.ops = &vc5_dbl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) vc5->clk_mul.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* Register PFD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) init.ops = &vc5_pfd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) parent_names[0] = clk_hw_get_name(&vc5->clk_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) vc5->clk_pfd.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Register PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) init.ops = &vc5_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) parent_names[0] = clk_hw_get_name(&vc5->clk_pfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) vc5->clk_pll.num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) vc5->clk_pll.vc5 = vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) vc5->clk_pll.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* Register FODs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) idx = vc5_map_index_to_output(vc5->chip_info->model, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) client->dev.of_node, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) init.ops = &vc5_fod_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) vc5->clk_fod[n].num = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) vc5->clk_fod[n].vc5 = vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) vc5->clk_fod[n].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* Register MUX-connected OUT0_I2C_SELB output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) init.ops = &vc5_clk_out_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) vc5->clk_out[0].num = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) vc5->clk_out[0].vc5 = vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) vc5->clk_out[0].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Register FOD-connected OUTx outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (n == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) parent_names[1] = clk_hw_get_name(&vc5->clk_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) parent_names[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) clk_hw_get_name(&vc5->clk_out[n - 1].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) client->dev.of_node, idx + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) init.ops = &vc5_clk_out_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) init.num_parents = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) vc5->clk_out[n].num = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) vc5->clk_out[n].vc5 = vc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) vc5->clk_out[n].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Fetch Clock Output configuration from DT (if specified) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ret = vc5_get_output_config(client, &vc5->clk_out[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) dev_err(&client->dev, "unable to add clk provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) err_clk_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev_err(&client->dev, "unable to register %s\n", init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) clk_unregister_fixed_rate(vc5->pin_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int vc5_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) of_clk_del_provider(client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) clk_unregister_fixed_rate(vc5->pin_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int __maybe_unused vc5_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) regcache_cache_only(vc5->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) regcache_mark_dirty(vc5->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static int __maybe_unused vc5_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) regcache_cache_only(vc5->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ret = regcache_sync(vc5->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) dev_err(dev, "Failed to restore register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static const struct vc5_chip_info idt_5p49v5923_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .model = IDT_VC5_5P49V5923,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .clk_fod_cnt = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .clk_out_cnt = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static const struct vc5_chip_info idt_5p49v5925_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .model = IDT_VC5_5P49V5925,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .clk_fod_cnt = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .clk_out_cnt = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const struct vc5_chip_info idt_5p49v5933_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .model = IDT_VC5_5P49V5933,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .clk_fod_cnt = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .clk_out_cnt = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .flags = VC5_HAS_INTERNAL_XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const struct vc5_chip_info idt_5p49v5935_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .model = IDT_VC5_5P49V5935,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .clk_fod_cnt = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .clk_out_cnt = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .flags = VC5_HAS_INTERNAL_XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static const struct vc5_chip_info idt_5p49v6901_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .model = IDT_VC6_5P49V6901,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .clk_fod_cnt = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .clk_out_cnt = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .flags = VC5_HAS_PFD_FREQ_DBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static const struct vc5_chip_info idt_5p49v6965_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .model = IDT_VC6_5P49V6965,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .clk_fod_cnt = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .clk_out_cnt = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .flags = VC5_HAS_BYPASS_SYNC_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const struct i2c_device_id vc5_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) { "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) MODULE_DEVICE_TABLE(i2c, vc5_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static const struct of_device_id clk_vc5_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static struct i2c_driver vc5_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .name = "vc5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .pm = &vc5_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .of_match_table = clk_vc5_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .probe = vc5_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .remove = vc5_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .id_table = vc5_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) module_i2c_driver(vc5_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) MODULE_DESCRIPTION("IDT VersaClock 5 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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