^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * U300 clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007-2012 ST-Ericsson AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Linus Walleij <linus.walleij@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_data/clk-u300.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* APP side SYSCON registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* CLK Control Register 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define U300_SYSCON_CCR (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* CLK Status Register 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define U300_SYSCON_CSR (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Reset lines for SLOW devices 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define U300_SYSCON_RSR (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Reset lines for FAST devices 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define U300_SYSCON_RFR (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Reset lines for the rest of the peripherals 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define U300_SYSCON_RRR (0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Clock enable for SLOW peripherals 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define U300_SYSCON_CESR (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Clock enable for FAST peripherals 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define U300_SYSCON_CEFR (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Clock enable for the rest of the peripherals 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define U300_SYSCON_CERR (0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Single block clock enable 16bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define U300_SYSCON_SBCER (0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Single block clock disable 16bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define U300_SYSCON_SBCDR (0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Same values as above for SBCER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Clock force SLOW peripherals 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define U300_SYSCON_CFSR (0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Clock force FAST peripherals 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define U300_SYSCON_CFFR (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Values not defined. Define if you want to use them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Clock force the rest of the peripherals 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define U300_SYSCON_CFRR (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* PLL208 Frequency Control 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define U300_SYSCON_PFCR (0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Power Management Control 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define U300_SYSCON_PMCR (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Reset Out 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define U300_SYSCON_RCR (0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* EMIF Slew Rate Control 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define U300_SYSCON_SRCLR (0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define U300_SYSCON_SRCLR_MASK (0x03FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define U300_SYSCON_SRCLR_VALUE (0x03FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* EMIF Clock Control Register 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define U300_SYSCON_ECCR (0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define U300_SYSCON_ECCR_MASK (0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* MMC/MSPRO frequency divider register 0 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define U300_SYSCON_MMF0R (0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define U300_SYSCON_MMF0R_MASK (0x00FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* MMC/MSPRO frequency divider register 1 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define U300_SYSCON_MMF1R (0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define U300_SYSCON_MMF1R_MASK (0x00FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define U300_SYSCON_MMCR (0x9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define U300_SYSCON_MMCR_MASK (0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define U300_SYSCON_S0CCR (0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define U300_SYSCON_S0CCR_SEL_MCLK (0x8 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define U300_SYSCON_S1CCR (0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define U300_SYSCON_S1CCR_SEL_MCLK (0x8 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* SYS_2_CLK_CONTROL third clock control 16 bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define U300_SYSCON_S2CCR (0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define U300_SYSCON_S2CCR_SEL_MCLK (0x8 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* SC_PLL_IRQ_CONTROL 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define U300_SYSCON_PICR (0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define U300_SYSCON_PICR_MASK (0x00FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* SC_PLL_IRQ_STATUS 16 bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define U300_SYSCON_PISR (0x0134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define U300_SYSCON_PISR_MASK (0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define U300_SYSCON_PICLR (0x0138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define U300_SYSCON_PICLR_MASK (0x000F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define U300_SYSCON_PICLR_RWMASK (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Clock activity observability register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define U300_SYSCON_C0OAR (0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define U300_SYSCON_C0OAR_MASK (0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define U300_SYSCON_C0OAR_VALUE (0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Clock activity observability register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define U300_SYSCON_C1OAR (0x144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define U300_SYSCON_C1OAR_MASK (0x3FFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define U300_SYSCON_C1OAR_VALUE (0x3FFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Clock activity observability register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define U300_SYSCON_C2OAR (0x148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define U300_SYSCON_C2OAR_MASK (0x0FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define U300_SYSCON_C2OAR_VALUE (0x0FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define U300_SYSCON_C2OAR_VC_CLK (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * The clocking hierarchy currently looks like this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * NOTE: the idea is NOT to show how the clocks are routed on the chip!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * The ideas is to show dependencies, so a clock higher up in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * hierarchy has to be on in order for another clock to be on. Now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * both CPU and DMA can actually be on top of the hierarchy, and that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * is not modeled currently. Instead we have the backbone AMBA bus on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * top. This bus cannot be programmed in any way but conceptually it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * needs to be active for the bridges and devices to transport data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Please be aware that a few clocks are hw controlled, which mean that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * the hw itself can turn on/off or change the rate of the clock when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * needed!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * AMBA bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * +- CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * +- FSMC NANDIF NAND Flash interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * +- SEMI Shared Memory interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * +- ISP Image Signal Processor (U335 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * +- CDS (U335 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * +- DMA Direct Memory Access Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * +- AAIF APP/ACC Interface (Mobile Scalable Link, MSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * +- APEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * +- VIDEO_ENC AVE2/3 Video Encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * +- XGAM Graphics Accelerator Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * +- AHB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * +- ahb:0 AHB Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * | +- ahb:1 INTCON Interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * | +- ahb:3 MSPRO Memory Stick Pro controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * | +- ahb:4 EMIF External Memory interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * +- fast:0 FAST bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * | +- fast:1 MMCSD MMC/SD card reader controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * | +- fast:2 I2S0 PCM I2S channel 0 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * | +- fast:3 I2S1 PCM I2S channel 1 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * | +- fast:4 I2C0 I2C channel 0 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * | +- fast:5 I2C1 I2C channel 1 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * | +- fast:6 SPI SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * | +- fast:7 UART1 Secondary UART (U335 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * +- slow:0 SLOW bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * +- slow:1 SYSCON (not possible to control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * +- slow:2 WDOG Watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * +- slow:3 UART0 primary UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * +- slow:4 TIMER_APP Application timer - used in Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * +- slow:5 KEYPAD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * +- slow:6 GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * +- slow:7 RTC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * +- slow:8 BT Bus Tracer (not used currently)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * +- slow:9 EH Event Handler (not used currently)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * +- slow:a TIMER_ACC Access style timer (not used currently)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * +- slow:b PPM (U335 only, what is that?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Global syscon virtual base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void __iomem *syscon_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * struct clk_syscon - U300 syscon clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * @hw: corresponding clock hardware entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * @hw_ctrld: whether this clock is hardware controlled (for refcount etc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * and does not need any magic pokes to be enabled/disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * @reset: state holder, whether this block's reset line is asserted or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * @res_reg: reset line enable/disable flag register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * @res_bit: bit for resetting or taking this consumer out of reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * @en_reg: clock line enable/disable flag register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * @en_bit: bit for enabling/disabling this consumer clock line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * @clk_val: magic value to poke in the register to enable/disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * this one clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct clk_syscon {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) bool hw_ctrld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) bool reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) void __iomem *res_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u8 res_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void __iomem *en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 en_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u16 clk_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static DEFINE_SPINLOCK(syscon_resetreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Reset control functions. We remember if a block has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * taken out of reset and don't remove the reset assertion again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * and vice versa. Currently we only remove resets so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * enablement function is defined out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void syscon_block_reset_enable(struct clk_syscon *sclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned long iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Not all blocks support resetting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (!sclk->res_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spin_lock_irqsave(&syscon_resetreg_lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) val = readw(sclk->res_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) val |= BIT(sclk->res_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) writew(val, sclk->res_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sclk->reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void syscon_block_reset_disable(struct clk_syscon *sclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned long iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Not all blocks support resetting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!sclk->res_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) spin_lock_irqsave(&syscon_resetreg_lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) val = readw(sclk->res_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) val &= ~BIT(sclk->res_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) writew(val, sclk->res_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sclk->reset = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int syscon_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct clk_syscon *sclk = to_syscon(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* If the block is in reset, bring it out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (sclk->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) syscon_block_reset_disable(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void syscon_clk_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct clk_syscon *sclk = to_syscon(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Please don't force the console into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* When unpreparing, force block into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (!sclk->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) syscon_block_reset_enable(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int syscon_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct clk_syscon *sclk = to_syscon(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Don't touch the hardware controlled clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (sclk->hw_ctrld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* These cannot be controlled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (sclk->clk_val == 0xFFFFU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void syscon_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct clk_syscon *sclk = to_syscon(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Don't touch the hardware controlled clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (sclk->hw_ctrld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (sclk->clk_val == 0xFFFFU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Please don't disable the console port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int syscon_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct clk_syscon *sclk = to_syscon(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* If no enable register defined, it's always-on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!sclk->en_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) val = readw(sclk->en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) val &= BIT(sclk->en_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return val ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static u16 syscon_get_perf(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) val = readw(syscon_vbase + U300_SYSCON_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) syscon_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct clk_syscon *sclk = to_syscon(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u16 perf = syscon_get_perf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) switch (sclk->clk_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case U300_SYSCON_SBCER_I2C0_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case U300_SYSCON_SBCER_I2C1_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case U300_SYSCON_SBCER_MMC_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case U300_SYSCON_SBCER_SPI_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* The FAST clocks have one progression */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) switch (perf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return parent_rate; /* 26 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case U300_SYSCON_SBCER_DMAC_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case U300_SYSCON_SBCER_NANDIF_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case U300_SYSCON_SBCER_XGAM_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* AMBA interconnect peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) switch (perf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 6500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 26000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return parent_rate; /* 52 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case U300_SYSCON_SBCER_SEMI_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case U300_SYSCON_SBCER_EMIF_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* EMIF speeds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) switch (perf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 52000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return 104000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case U300_SYSCON_SBCER_CPU_CLK_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* And the fast CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) switch (perf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 52000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return 104000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return parent_rate; /* 208 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * The SLOW clocks and default just inherit the rate of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * their parent (typically PLL13 13 MHz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct clk_syscon *sclk = to_syscon(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* We really only support setting the rate of the CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (rate <= 13000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (rate <= 52000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 52000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (rate <= 104000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 104000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 208000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int syscon_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct clk_syscon *sclk = to_syscon(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* We only support setting the rate of the CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case 13000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case 52000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case 104000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case 208000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val |= readw(syscon_vbase + U300_SYSCON_CCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) writew(val, syscon_vbase + U300_SYSCON_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const struct clk_ops syscon_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .prepare = syscon_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .unprepare = syscon_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .enable = syscon_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .disable = syscon_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .is_enabled = syscon_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .recalc_rate = syscon_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .round_rate = syscon_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .set_rate = syscon_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) syscon_clk_register(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) bool hw_ctrld,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) void __iomem *res_reg, u8 res_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) void __iomem *en_reg, u8 en_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u16 clk_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct clk_syscon *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!sclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) init.ops = &syscon_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) sclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) sclk->hw_ctrld = hw_ctrld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Assume the block is in reset at registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) sclk->reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) sclk->res_reg = res_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) sclk->res_bit = res_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) sclk->en_reg = en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) sclk->en_bit = en_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sclk->clk_val = clk_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) hw = &sclk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) kfree(sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define U300_CLK_TYPE_SLOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define U300_CLK_TYPE_FAST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define U300_CLK_TYPE_REST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * struct u300_clock - defines the bits and pieces for a certain clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * @type: the clock type, slow fast or rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * @id: the bit in the slow/fast/rest register for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * @hw_ctrld: whether the clock is hardware controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * @clk_val: a value to poke in the one-write enable/disable registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct u300_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) bool hw_ctrld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u16 clk_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static struct u300_clock const u300_clk_lookup[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .type = U300_CLK_TYPE_REST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .id = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .hw_ctrld = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .type = U300_CLK_TYPE_REST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .id = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .hw_ctrld = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .type = U300_CLK_TYPE_REST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .id = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .type = U300_CLK_TYPE_REST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .id = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .type = U300_CLK_TYPE_REST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .id = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .hw_ctrld = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .type = U300_CLK_TYPE_REST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .id = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .type = U300_CLK_TYPE_REST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .id = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .hw_ctrld = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .type = U300_CLK_TYPE_REST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .id = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* INTCON: cannot be enabled, just taken out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .clk_val = 0xFFFFU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .type = U300_CLK_TYPE_FAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .hw_ctrld = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .type = U300_CLK_TYPE_FAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .type = U300_CLK_TYPE_FAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .type = U300_CLK_TYPE_FAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .id = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .type = U300_CLK_TYPE_FAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .id = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .type = U300_CLK_TYPE_SLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .hw_ctrld = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .type = U300_CLK_TYPE_SLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .type = U300_CLK_TYPE_SLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .id = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .type = U300_CLK_TYPE_SLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .id = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .hw_ctrld = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* No clock enable register bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .clk_val = 0xFFFFU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .type = U300_CLK_TYPE_SLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .id = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .type = U300_CLK_TYPE_SLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .id = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .hw_ctrld = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static void __init of_u300_syscon_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct clk_hw *hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) const char *clk_name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) void __iomem *res_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) void __iomem *en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u32 clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (of_property_read_u32(np, "clock-type", &clk_type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) __func__, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (of_property_read_u32(np, "clock-id", &clk_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) __func__, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) switch (clk_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case U300_CLK_TYPE_SLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) res_reg = syscon_vbase + U300_SYSCON_RSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) en_reg = syscon_vbase + U300_SYSCON_CESR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case U300_CLK_TYPE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) res_reg = syscon_vbase + U300_SYSCON_RFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) en_reg = syscon_vbase + U300_SYSCON_CEFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case U300_CLK_TYPE_REST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) res_reg = syscon_vbase + U300_SYSCON_RRR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) en_reg = syscon_vbase + U300_SYSCON_CERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) pr_err("unknown clock type %x specified\n", clk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) const struct u300_clock *u3clk = &u300_clk_lookup[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (u3clk->type == clk_type && u3clk->id == clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) hw = syscon_clk_register(NULL, clk_name, parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) 0, u3clk->hw_ctrld,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) res_reg, u3clk->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) en_reg, u3clk->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u3clk->clk_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (!IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * Some few system clocks - device tree does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * represent clocks without a corresponding device node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * for now we add these three clocks here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) clk_hw_register_clkdev(hw, NULL, "pl172");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) clk_hw_register_clkdev(hw, NULL, "semi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) clk_hw_register_clkdev(hw, NULL, "intcon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * @hw: corresponding clock hardware entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * @is_mspro: if this is the memory stick clock rather than MMC/SD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct clk_mclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) bool is_mspro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define to_mclk(_hw) container_of(_hw, struct clk_mclk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int mclk_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct clk_mclk *mclk = to_mclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* The MMC and MSPRO clocks need some special set-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!mclk->is_mspro) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Set default MMC clock divisor to 18.9 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) val = readw(syscon_vbase + U300_SYSCON_MMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Disable the MMC feedback clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Disable MSPRO frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) writew(val, syscon_vbase + U300_SYSCON_MMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) val = readw(syscon_vbase + U300_SYSCON_MMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* Disable the MMC feedback clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Enable MSPRO frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) writew(val, syscon_vbase + U300_SYSCON_MMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mclk_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u16 perf = syscon_get_perf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) switch (perf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * Here, the 208 MHz PLL gets shut down and the always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * on 13 MHz PLL used for RTC etc kicks into use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * This clock is under program control. The register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * divided in two nybbles, bit 7-4 gives cycles-1 to count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * high, bit 3-0 gives cycles-1 to count low. Distribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * these with no more than 1 cycle difference between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * low and high and add low and high to get the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * divisor. The base PLL is 208 MHz. Writing 0x00 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * divide by 1 and 1 so the highest frequency possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * is 104 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * e.g. 0x54 =>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) U300_SYSCON_MMF0R_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) case 0x0054:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return 18900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case 0x0044:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return 20800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) case 0x0043:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return 23100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) case 0x0033:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return 26000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) case 0x0032:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return 29700000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case 0x0022:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return 34700000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) case 0x0021:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return 41600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) case 0x0011:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return 52000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case 0x0000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 104000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (rate <= 18900000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return 18900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (rate <= 20800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 20800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (rate <= 23100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return 23100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (rate <= 26000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return 26000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (rate <= 29700000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return 29700000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (rate <= 34700000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return 34700000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (rate <= 41600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return 41600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Highest rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 52000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static int mclk_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case 18900000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) val = 0x0054;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case 20800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) val = 0x0044;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case 23100000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) val = 0x0043;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) val = 0x0033;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case 29700000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) val = 0x0032;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case 34700000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) val = 0x0022;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case 41600000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) val = 0x0021;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case 52000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) val = 0x0011;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) case 104000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) val = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ~U300_SYSCON_MMF0R_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const struct clk_ops mclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .prepare = mclk_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .recalc_rate = mclk_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .round_rate = mclk_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .set_rate = mclk_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) mclk_clk_register(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) const char *parent_name, bool is_mspro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct clk_mclk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!mclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) init.name = "mclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) init.ops = &mclk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) mclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) mclk->is_mspro = is_mspro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) hw = &mclk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) kfree(mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static void __init of_u300_syscon_mclk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) const char *clk_name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) hw = mclk_clk_register(NULL, clk_name, parent_name, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (!IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const struct of_device_id u300_clk_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .compatible = "fixed-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .data = of_fixed_clk_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .compatible = "fixed-factor-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .data = of_fixed_factor_clk_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .compatible = "stericsson,u300-syscon-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .data = of_u300_syscon_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .compatible = "stericsson,u300-syscon-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .data = of_u300_syscon_mclk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) void __init u300_clk_init(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) syscon_vbase = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Set system to run at PLL208, max performance, a known state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) val = readw(syscon_vbase + U300_SYSCON_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) writew(val, syscon_vbase + U300_SYSCON_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* Wait for the PLL208 to lock if not locked in yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) while (!(readw(syscon_vbase + U300_SYSCON_CSR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) U300_SYSCON_CSR_PLL208_LOCK_IND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* Power management enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) val = readw(syscon_vbase + U300_SYSCON_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) writew(val, syscon_vbase + U300_SYSCON_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) of_clk_init(u300_clk_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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