^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Olivier Bideau <olivier.bideau@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/stm32mp1-clks.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static DEFINE_SPINLOCK(rlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RCC_OCENSETR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RCC_HSICFGR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RCC_RDLSICR 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RCC_PLL1CR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RCC_PLL1CFGR1 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RCC_PLL1CFGR2 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RCC_PLL2CR 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RCC_PLL2CFGR1 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RCC_PLL2CFGR2 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RCC_PLL3CR 0x880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RCC_PLL3CFGR1 0x884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RCC_PLL3CFGR2 0x888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RCC_PLL4CR 0x894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RCC_PLL4CFGR1 0x898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RCC_PLL4CFGR2 0x89C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RCC_APB1ENSETR 0xA00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RCC_APB2ENSETR 0xA08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RCC_APB3ENSETR 0xA10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RCC_APB4ENSETR 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RCC_APB5ENSETR 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RCC_AHB2ENSETR 0xA18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RCC_AHB3ENSETR 0xA20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RCC_AHB4ENSETR 0xA28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RCC_AHB5ENSETR 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RCC_AHB6ENSETR 0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RCC_AHB6LPENSETR 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RCC_RCK12SELR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RCC_RCK3SELR 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RCC_RCK4SELR 0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RCC_MPCKSELR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RCC_ASSCKSELR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RCC_MSSCKSELR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RCC_SPI6CKSELR 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RCC_SDMMC12CKSELR 0x8F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RCC_SDMMC3CKSELR 0x8F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RCC_FMCCKSELR 0x904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RCC_I2C46CKSELR 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RCC_I2C12CKSELR 0x8C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RCC_I2C35CKSELR 0x8C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RCC_UART1CKSELR 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RCC_QSPICKSELR 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RCC_ETHCKSELR 0x8FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RCC_RNG1CKSELR 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RCC_RNG2CKSELR 0x920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RCC_GPUCKSELR 0x938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RCC_USBCKSELR 0x91C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RCC_STGENCKSELR 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RCC_SPDIFCKSELR 0x914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RCC_SPI2S1CKSELR 0x8D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RCC_SPI2S23CKSELR 0x8DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RCC_SPI2S45CKSELR 0x8E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RCC_CECCKSELR 0x918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RCC_LPTIM1CKSELR 0x934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RCC_LPTIM23CKSELR 0x930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RCC_LPTIM45CKSELR 0x92C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RCC_UART24CKSELR 0x8E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RCC_UART35CKSELR 0x8EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RCC_UART6CKSELR 0x8E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RCC_UART78CKSELR 0x8F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RCC_FDCANCKSELR 0x90C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RCC_SAI1CKSELR 0x8C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RCC_SAI2CKSELR 0x8CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RCC_SAI3CKSELR 0x8D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RCC_SAI4CKSELR 0x8D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RCC_ADCCKSELR 0x928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RCC_MPCKDIVR 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RCC_DSICKSELR 0x924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RCC_CPERCKSELR 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RCC_MCO1CFGR 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RCC_MCO2CFGR 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RCC_BDCR 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RCC_AXIDIVR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RCC_MCUDIVR 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RCC_APB1DIVR 0x834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RCC_APB2DIVR 0x838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RCC_APB3DIVR 0x83C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RCC_APB4DIVR 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RCC_APB5DIVR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RCC_TIMG1PRER 0x828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RCC_TIMG2PRER 0x82C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RCC_RTCDIVR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RCC_DBGCFGR 0x80C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RCC_CLR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const char * const ref12_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "ck_hsi", "ck_hse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const ref3_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "ck_hsi", "ck_hse", "ck_csi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const char * const ref4_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "ck_hsi", "ck_hse", "ck_csi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const char * const cpu_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "ck_hsi", "ck_hse", "pll1_p"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const char * const axi_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "ck_hsi", "ck_hse", "pll2_p"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const char * const per_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "ck_hsi", "ck_csi", "ck_hse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const char * const mcu_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "ck_hsi", "ck_hse", "ck_csi", "pll3_p"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const char * const sdmmc12_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const char * const sdmmc3_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "ck_mcu", "pll3_r", "pll4_p", "ck_hsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const char * const fmc_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "ck_axi", "pll3_r", "pll4_p", "ck_per"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const char * const qspi_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "ck_axi", "pll3_r", "pll4_p", "ck_per"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const char * const eth_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "pll4_p", "pll3_q"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const char * const rng_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const char * const usbphy_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "ck_hse", "pll4_r", "clk-hse-div2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const char * const usbo_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "pll4_r", "ck_usbo_48m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const char * const stgen_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "ck_hsi", "ck_hse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const char * const spdif_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "pll4_p", "pll3_q", "ck_hsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const char * const spi123_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const char * const spi45_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const char * const spi6_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "pclk5", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "pll3_q"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const char * const cec_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "ck_lse", "ck_lsi", "ck_csi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const char * const i2c12_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "pclk1", "pll4_r", "ck_hsi", "ck_csi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const char * const i2c35_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "pclk1", "pll4_r", "ck_hsi", "ck_csi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const char * const i2c46_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "pclk5", "pll3_q", "ck_hsi", "ck_csi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const char * const lptim1_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const char * const lptim23_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char * const lptim45_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const char * const usart1_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const char * const usart234578_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const char * const usart6_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const char * const fdcan_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "ck_hse", "pll3_q", "pll4_q", "pll4_r"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char * const sai_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const char * const sai2_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const char * const adc12_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "pll4_r", "ck_per", "pll3_q"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const char * const dsi_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "ck_dsi_phy", "pll4_p"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const char * const rtc_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "off", "ck_lse", "ck_lsi", "ck_hse_rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const char * const mco1_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char * const mco2_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const char * const ck_trace_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "ck_axi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct clk_div_table axi_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct clk_div_table mcu_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct clk_div_table apb_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct clk_div_table ck_trace_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MAX_MUX_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct stm32_mmux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 nbr_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct clk_hw *hws[MAX_MUX_CLK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct stm32_clk_mmux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct clk_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct stm32_mmux *mmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct stm32_mgate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 nbr_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct stm32_clk_mgate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct stm32_mgate *mgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct clock_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct clk_hw * (*func)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) const struct clock_config *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define NO_ID ~0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct gate_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 reg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct fixed_factor_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct div_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 reg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) const struct clk_div_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct mux_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 reg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct stm32_gate_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct gate_cfg *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct stm32_mgate *mgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) const struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct stm32_div_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct div_cfg *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) const struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct stm32_mux_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct mux_cfg *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct stm32_mmux *mmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* STM32 Composite clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct stm32_composite_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) const struct stm32_gate_cfg *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) const struct stm32_div_cfg *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) const struct stm32_mux_cfg *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) _clk_hw_register_gate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) const struct clock_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct gate_cfg *gate_cfg = cfg->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return clk_hw_register_gate(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) cfg->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) cfg->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) cfg->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) gate_cfg->reg_off + base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) gate_cfg->bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) gate_cfg->gate_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) _clk_hw_register_fixed_factor(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) const struct clock_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct fixed_factor_cfg *ff_cfg = cfg->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) cfg->flags, ff_cfg->mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ff_cfg->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) _clk_hw_register_divider_table(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) const struct clock_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct div_cfg *div_cfg = cfg->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return clk_hw_register_divider_table(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cfg->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cfg->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cfg->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) div_cfg->reg_off + base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) div_cfg->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) div_cfg->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) div_cfg->div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) div_cfg->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) _clk_hw_register_mux(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) const struct clock_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct mux_cfg *mux_cfg = cfg->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) cfg->num_parents, cfg->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mux_cfg->reg_off + base, mux_cfg->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mux_cfg->width, mux_cfg->mux_flags, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* MP1 Gate clock with set & clear registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int mp1_gate_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!clk_gate_ops.is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) clk_gate_ops.enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void mp1_gate_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (clk_gate_ops.is_enabled(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const struct clk_ops mp1_gate_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .enable = mp1_gate_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .disable = mp1_gate_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .is_enabled = clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct clk_hw *_get_stm32_mux(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) const struct stm32_mux_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct stm32_clk_mmux *mmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct clk_hw *mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (cfg->mmux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!mmux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mmux->mux.reg = cfg->mux->reg_off + base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mmux->mux.shift = cfg->mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mmux->mux.mask = (1 << cfg->mux->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mmux->mux.flags = cfg->mux->mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mmux->mux.table = cfg->mux->table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) mmux->mux.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) mmux->mmux = cfg->mmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mux_hw = &mmux->mux.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) mux->reg = cfg->mux->reg_off + base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mux->shift = cfg->mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mux->mask = (1 << cfg->mux->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mux->flags = cfg->mux->mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mux->table = cfg->mux->table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) mux->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mux_hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static struct clk_hw *_get_stm32_div(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) const struct stm32_div_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct clk_divider *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) div = kzalloc(sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) div->reg = cfg->div->reg_off + base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) div->shift = cfg->div->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) div->width = cfg->div->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) div->flags = cfg->div->div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) div->table = cfg->div->table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) div->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return &div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) _get_stm32_gate(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) const struct stm32_gate_cfg *cfg, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct stm32_clk_mgate *mgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct clk_hw *gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (cfg->mgate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!mgate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mgate->gate.reg = cfg->gate->reg_off + base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mgate->gate.bit_idx = cfg->gate->bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) mgate->gate.flags = cfg->gate->gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mgate->gate.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mgate->mask = BIT(cfg->mgate->nbr_clk++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mgate->mgate = cfg->mgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) gate_hw = &mgate->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) gate->reg = cfg->gate->reg_off + base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) gate->bit_idx = cfg->gate->bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) gate->flags = cfg->gate->gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) gate->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) gate_hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) clk_stm32_register_gate_ops(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) const struct stm32_gate_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct clk_init_data init = { NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) init.ops = &clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (cfg->ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) init.ops = cfg->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) hw = _get_stm32_gate(base, cfg, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) hw->init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clk_stm32_register_composite(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) const char *name, const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int num_parents, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) const struct stm32_composite_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned long flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) const struct clk_ops *mux_ops, *div_ops, *gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct clk_hw *mux_hw, *div_hw, *gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mux_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) div_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) gate_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mux_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) div_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) gate_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (cfg->mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mux_hw = _get_stm32_mux(base, cfg->mux, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!IS_ERR(mux_hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mux_ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (cfg->mux->ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mux_ops = cfg->mux->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (cfg->div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) div_hw = _get_stm32_div(base, cfg->div, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!IS_ERR(div_hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) div_ops = &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (cfg->div->ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) div_ops = cfg->div->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (cfg->gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) gate_hw = _get_stm32_gate(base, cfg->gate, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (!IS_ERR(gate_hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) gate_ops = &clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (cfg->gate->ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) gate_ops = cfg->gate->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return clk_hw_register_composite(dev, name, parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mux_hw, mux_ops, div_hw, div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) gate_hw, gate_ops, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int mp1_mgate_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) clk_mgate->mgate->flag |= clk_mgate->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mp1_gate_clk_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static void mp1_mgate_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) clk_mgate->mgate->flag &= ~clk_mgate->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (clk_mgate->mgate->flag == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mp1_gate_clk_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const struct clk_ops mp1_mgate_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .enable = mp1_mgate_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .disable = mp1_mgate_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .is_enabled = clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define to_clk_mmux(_mux) container_of(_mux, struct stm32_clk_mmux, mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static u8 clk_mmux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return clk_mux_ops.get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct clk_mux *mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct stm32_clk_mmux *clk_mmux = to_clk_mmux(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct clk_hw *hwp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int ret, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = clk_mux_ops.set_parent(hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) hwp = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) for (n = 0; n < clk_mmux->mmux->nbr_clk; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (clk_mmux->mmux->hws[n] != hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) clk_hw_reparent(clk_mmux->mmux->hws[n], hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const struct clk_ops clk_mmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .get_parent = clk_mmux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .set_parent = clk_mmux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* STM32 PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct stm32_pll_obj {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* lock pll enable/disable registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define PLL_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define PLL_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define DIVN_MASK 0x1FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define DIVM_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define DIVM_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define DIVN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define FRAC_OFFSET 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define FRAC_MASK 0x1FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define FRAC_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define FRACLE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int __pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return readl_relaxed(clk_elem->reg) & PLL_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define TIMEOUT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) unsigned int timeout = TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int bit_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) spin_lock_irqsave(clk_elem->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (__pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) reg = readl_relaxed(clk_elem->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) reg |= PLL_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) writel_relaxed(reg, clk_elem->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* We can't use readl_poll_timeout() because we can be blocked if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * someone enables this clock before clocksource changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * Only jiffies counter is available. Jiffies are incremented by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * interruptions and enable op does not allow to be interrupted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (bit_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) udelay(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) } while (bit_status && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) spin_unlock_irqrestore(clk_elem->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return bit_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) spin_lock_irqsave(clk_elem->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) reg = readl_relaxed(clk_elem->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) reg &= ~PLL_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) writel_relaxed(reg, clk_elem->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) spin_unlock_irqrestore(clk_elem->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static u32 pll_frac_val(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 reg, frac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (reg & FRACLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) frac = (reg >> FRAC_SHIFT) & FRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static unsigned long pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 frac, divm, divn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u64 rate, rate_frac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) reg = readl_relaxed(clk_elem->reg + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) rate = (u64)parent_rate * divn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) do_div(rate, divm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) frac = pll_frac_val(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (frac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) rate_frac = (u64)parent_rate * (u64)frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) do_div(rate_frac, (divm * 8192));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return rate + rate_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) spin_lock_irqsave(clk_elem->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ret = __pll_is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) spin_unlock_irqrestore(clk_elem->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const struct clk_ops pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .enable = pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .disable = pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .recalc_rate = pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .is_enabled = pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct stm32_pll_obj *element;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) element = kzalloc(sizeof(*element), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (!element)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) init.ops = &pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) element->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) element->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) element->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) hw = &element->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) err = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) kfree(element);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Kernel Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct timer_cker {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* lock the kernel output divider register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) void __iomem *apbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) void __iomem *timpre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define to_timer_cker(_hw) container_of(_hw, struct timer_cker, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define APB_DIV_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define TIM_PRE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct timer_cker *tim_ker = to_timer_cker(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u32 prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) unsigned int mult = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (prescaler < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) mult = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (rate / parent_rate >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) mult = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static long timer_ker_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned long factor = __bestmult(hw, rate, *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return *parent_rate * factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int timer_ker_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct timer_cker *tim_ker = to_timer_cker(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) unsigned long factor = __bestmult(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) spin_lock_irqsave(tim_ker->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) switch (factor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) writel_relaxed(0, tim_ker->timpre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) writel_relaxed(1, tim_ker->timpre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) spin_unlock_irqrestore(tim_ker->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct timer_cker *tim_ker = to_timer_cker(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u32 prescaler, timpre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (!prescaler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mul = (timpre + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return parent_rate * mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const struct clk_ops timer_ker_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .recalc_rate = timer_ker_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .round_rate = timer_ker_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .set_rate = timer_ker_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) void __iomem *apbdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) void __iomem *timpre,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct timer_cker *tim_ker;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) tim_ker = kzalloc(sizeof(*tim_ker), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (!tim_ker)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) init.ops = &timer_ker_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) tim_ker->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) tim_ker->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) tim_ker->apbdiv = apbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) tim_ker->timpre = timpre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) hw = &tim_ker->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) err = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) kfree(tim_ker);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct stm32_pll_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static struct clk_hw *_clk_register_pll(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) const struct clock_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return clk_register_pll(dev, cfg->name, cfg->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) base + stm_pll_cfg->offset, cfg->flags, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct stm32_cktim_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) u32 offset_apbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) u32 offset_timpre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static struct clk_hw *_clk_register_cktim(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) const struct clock_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) cktim_cfg->offset_apbdiv + base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) cktim_cfg->offset_timpre + base, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) _clk_stm32_register_gate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) const struct clock_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return clk_stm32_register_gate_ops(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) cfg->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) cfg->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) cfg->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) cfg->cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) _clk_stm32_register_composite(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) const struct clock_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) cfg->num_parents, base, cfg->cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) cfg->flags, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .id = _id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .parent_name = _parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .cfg = &(struct gate_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .reg_off = _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .bit_idx = _bit_idx,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .gate_flags = _gate_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .func = _clk_hw_register_gate,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .id = _id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .parent_name = _parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .cfg = &(struct fixed_factor_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .mult = _mult,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .div = _div,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .func = _clk_hw_register_fixed_factor,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) _div_flags, _div_table)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .id = _id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .parent_name = _parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .cfg = &(struct div_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .reg_off = _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .shift = _shift,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .width = _width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .div_flags = _div_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .table = _div_table,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .func = _clk_hw_register_divider_table,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) _div_flags, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .id = _id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .parent_names = _parents,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .num_parents = ARRAY_SIZE(_parents),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .cfg = &(struct mux_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .reg_off = _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .shift = _shift,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .width = _width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .mux_flags = _mux_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .func = _clk_hw_register_mux,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define PLL(_id, _name, _parent, _flags, _offset)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .id = _id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .parent_name = _parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .cfg = &(struct stm32_pll_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .offset = _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .func = _clk_register_pll,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define STM32_CKTIM(_name, _parent, _flags, _offset_apbdiv, _offset_timpre)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .id = NO_ID,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .parent_name = _parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .cfg = &(struct stm32_cktim_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .offset_apbdiv = _offset_apbdiv,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .offset_timpre = _offset_timpre,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .func = _clk_register_cktim,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) GATE_MP1(_id, _name, _parent, CLK_SET_RATE_PARENT,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) _offset_set, _bit_idx, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* STM32 GATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define STM32_GATE(_id, _name, _parent, _flags, _gate)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .id = _id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .parent_name = _parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .cfg = (struct stm32_gate_cfg *) {_gate},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .func = _clk_stm32_register_gate,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) (&(struct stm32_gate_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) &(struct gate_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .reg_off = _gate_offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .bit_idx = _gate_bit_idx,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .gate_flags = _gate_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .mgate = _mgate,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .ops = _ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define _STM32_MGATE(_mgate)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) (&per_gate_cfg[_mgate])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) NULL, NULL)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) NULL, &mp1_gate_clk_ops)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define _MGATE_MP1(_mgate)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .gate = &per_gate_cfg[_mgate]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) STM32_GATE(_id, _name, _parent, _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) _GATE_MP1(_offset, _bit_idx, _gate_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) STM32_GATE(_id, _name, _parent, _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) _STM32_MGATE(_mgate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define _STM32_DIV(_div_offset, _div_shift, _div_width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) _div_flags, _div_table, _ops)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .div = &(struct stm32_div_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) &(struct div_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .reg_off = _div_offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .shift = _div_shift,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .width = _div_width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .div_flags = _div_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .table = _div_table,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .ops = _ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) _STM32_DIV(_div_offset, _div_shift, _div_width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) _div_flags, _div_table, NULL)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .mux = &(struct stm32_mux_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) &(struct mux_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .reg_off = _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .shift = _shift,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .width = _width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .mux_flags = _mux_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .table = NULL,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .mmux = _mmux,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .ops = _ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define _MUX(_offset, _shift, _width, _mux_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define _MMUX(_mmux) .mux = &ker_mux_cfg[_mmux]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define PARENT(_parent) ((const char *[]) { _parent})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define _NO_MUX .mux = NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define _NO_DIV .div = NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define _NO_GATE .gate = NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .id = _id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .parent_names = _parents,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .num_parents = ARRAY_SIZE(_parents),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .cfg = &(struct stm32_composite_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) _gate,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) _mux,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) _div,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .func = _clk_stm32_register_composite,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define PCLK(_id, _name, _parent, _flags, _mgate)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) MGATE_MP1(_id, _name, _parent, _flags, _mgate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) CLK_SET_RATE_NO_REPARENT | _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) _MGATE_MP1(_mgate),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) _MMUX(_mmux),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) _NO_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) G_SAI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) G_SAI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) G_SAI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) G_SAI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) G_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) G_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) G_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) G_SPI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) G_SPI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) G_SPI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) G_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) G_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) G_I2C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) G_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) G_I2C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) G_I2C5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) G_I2C6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) G_USART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) G_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) G_USART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) G_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) G_USART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) G_USART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) G_UART7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) G_UART8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) G_LPTIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) G_LPTIM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) G_LPTIM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) G_LPTIM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) G_LPTIM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) G_LTDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) G_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) G_QSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) G_FMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) G_SDMMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) G_SDMMC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) G_SDMMC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) G_USBO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) G_USBPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) G_RNG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) G_RNG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) G_FDCAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) G_DAC12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) G_CEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) G_ADC12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) G_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) G_STGEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) G_DFSDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) G_ADFSDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) G_TIM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) G_TIM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) G_TIM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) G_TIM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) G_TIM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) G_TIM7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) G_TIM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) G_TIM13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) G_TIM14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) G_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) G_TIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) G_TIM8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) G_TIM15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) G_TIM16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) G_TIM17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) G_SYSCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) G_VREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) G_TMPSENS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) G_PMBCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) G_HDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) G_IWDG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) G_STGENRO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) G_DMA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) G_DMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) G_DMAMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) G_DCMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) G_CRYP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) G_HASH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) G_CRC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) G_HSEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) G_IPCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) G_GPIOA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) G_GPIOB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) G_GPIOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) G_GPIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) G_GPIOE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) G_GPIOF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) G_GPIOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) G_GPIOH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) G_GPIOI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) G_GPIOJ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) G_GPIOK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) G_MDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) G_ETHCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) G_ETHTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) G_ETHRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) G_ETHMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) G_CRC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) G_USBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) G_ETHSTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) G_RTCAPB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) G_TZC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) G_TZC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) G_TZPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) G_IWDG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) G_BSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) G_GPIOZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) G_CRYP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) G_HASH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) G_BKPSRAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) G_DDRPERFM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) G_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static struct stm32_mgate mp1_mgate[G_LAST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) _mgate, _ops)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) [_id] = {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) &(struct gate_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .reg_off = _gate_offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .bit_idx = _gate_bit_idx,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .gate_flags = _gate_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .mgate = _mgate,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .ops = _ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) NULL, &mp1_gate_clk_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define K_MGATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) &mp1_mgate[_id], &mp1_mgate_clk_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* Peripheral gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* Multi gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) K_MGATE(G_CEC, RCC_APB1ENSETR, 27, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) K_MGATE(G_SPDIF, RCC_APB1ENSETR, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) K_MGATE(G_I2C5, RCC_APB1ENSETR, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) K_MGATE(G_I2C3, RCC_APB1ENSETR, 23, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) K_MGATE(G_I2C2, RCC_APB1ENSETR, 22, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) K_MGATE(G_I2C1, RCC_APB1ENSETR, 21, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) K_MGATE(G_UART8, RCC_APB1ENSETR, 19, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) K_MGATE(G_UART7, RCC_APB1ENSETR, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) K_MGATE(G_UART5, RCC_APB1ENSETR, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) K_MGATE(G_UART4, RCC_APB1ENSETR, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) K_MGATE(G_USART3, RCC_APB1ENSETR, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) K_MGATE(G_USART2, RCC_APB1ENSETR, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) K_MGATE(G_SPI3, RCC_APB1ENSETR, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) K_MGATE(G_SPI2, RCC_APB1ENSETR, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) K_MGATE(G_LPTIM1, RCC_APB1ENSETR, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) K_GATE(G_TIM14, RCC_APB1ENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) K_GATE(G_TIM13, RCC_APB1ENSETR, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) K_GATE(G_TIM12, RCC_APB1ENSETR, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) K_GATE(G_TIM7, RCC_APB1ENSETR, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) K_GATE(G_TIM6, RCC_APB1ENSETR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) K_GATE(G_TIM5, RCC_APB1ENSETR, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) K_GATE(G_TIM4, RCC_APB1ENSETR, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) K_GATE(G_TIM3, RCC_APB1ENSETR, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) K_GATE(G_TIM2, RCC_APB1ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) K_MGATE(G_FDCAN, RCC_APB2ENSETR, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) K_GATE(G_ADFSDM, RCC_APB2ENSETR, 21, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) K_GATE(G_DFSDM, RCC_APB2ENSETR, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) K_MGATE(G_SAI3, RCC_APB2ENSETR, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) K_MGATE(G_SAI2, RCC_APB2ENSETR, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) K_MGATE(G_SAI1, RCC_APB2ENSETR, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) K_MGATE(G_USART6, RCC_APB2ENSETR, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) K_MGATE(G_SPI5, RCC_APB2ENSETR, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) K_MGATE(G_SPI4, RCC_APB2ENSETR, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) K_MGATE(G_SPI1, RCC_APB2ENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) K_GATE(G_TIM17, RCC_APB2ENSETR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) K_GATE(G_TIM16, RCC_APB2ENSETR, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) K_GATE(G_TIM15, RCC_APB2ENSETR, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) K_GATE(G_TIM8, RCC_APB2ENSETR, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) K_GATE(G_TIM1, RCC_APB2ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) K_GATE(G_HDP, RCC_APB3ENSETR, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) K_GATE(G_PMBCTRL, RCC_APB3ENSETR, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) K_GATE(G_TMPSENS, RCC_APB3ENSETR, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) K_GATE(G_VREF, RCC_APB3ENSETR, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) K_GATE(G_SYSCFG, RCC_APB3ENSETR, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) K_MGATE(G_SAI4, RCC_APB3ENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) K_MGATE(G_LPTIM5, RCC_APB3ENSETR, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) K_MGATE(G_LPTIM4, RCC_APB3ENSETR, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) K_MGATE(G_LPTIM3, RCC_APB3ENSETR, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) K_MGATE(G_LPTIM2, RCC_APB3ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) K_GATE(G_STGENRO, RCC_APB4ENSETR, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) K_MGATE(G_USBPHY, RCC_APB4ENSETR, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) K_GATE(G_IWDG2, RCC_APB4ENSETR, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) K_GATE(G_DDRPERFM, RCC_APB4ENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) K_MGATE(G_DSI, RCC_APB4ENSETR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) K_MGATE(G_LTDC, RCC_APB4ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) K_GATE(G_STGEN, RCC_APB5ENSETR, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) K_GATE(G_TZC2, RCC_APB5ENSETR, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) K_GATE(G_TZC1, RCC_APB5ENSETR, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) K_MGATE(G_I2C4, RCC_APB5ENSETR, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) K_MGATE(G_SPI6, RCC_APB5ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) K_MGATE(G_SDMMC3, RCC_AHB2ENSETR, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) K_MGATE(G_USBO, RCC_AHB2ENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) K_MGATE(G_ADC12, RCC_AHB2ENSETR, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) K_GATE(G_DMAMUX, RCC_AHB2ENSETR, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) K_GATE(G_DMA2, RCC_AHB2ENSETR, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) K_GATE(G_DMA1, RCC_AHB2ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) K_GATE(G_IPCC, RCC_AHB3ENSETR, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) K_GATE(G_HSEM, RCC_AHB3ENSETR, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) K_GATE(G_CRC2, RCC_AHB3ENSETR, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) K_MGATE(G_RNG2, RCC_AHB3ENSETR, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) K_GATE(G_HASH2, RCC_AHB3ENSETR, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) K_GATE(G_CRYP2, RCC_AHB3ENSETR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) K_GATE(G_DCMI, RCC_AHB3ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) K_GATE(G_GPIOK, RCC_AHB4ENSETR, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) K_GATE(G_GPIOJ, RCC_AHB4ENSETR, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) K_GATE(G_GPIOI, RCC_AHB4ENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) K_GATE(G_GPIOH, RCC_AHB4ENSETR, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) K_GATE(G_GPIOG, RCC_AHB4ENSETR, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) K_GATE(G_GPIOF, RCC_AHB4ENSETR, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) K_GATE(G_GPIOE, RCC_AHB4ENSETR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) K_GATE(G_GPIOD, RCC_AHB4ENSETR, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) K_GATE(G_GPIOC, RCC_AHB4ENSETR, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) K_GATE(G_GPIOB, RCC_AHB4ENSETR, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) K_GATE(G_GPIOA, RCC_AHB4ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) K_GATE(G_BKPSRAM, RCC_AHB5ENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) K_MGATE(G_RNG1, RCC_AHB5ENSETR, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) K_GATE(G_HASH1, RCC_AHB5ENSETR, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) K_GATE(G_CRYP1, RCC_AHB5ENSETR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) K_GATE(G_GPIOZ, RCC_AHB5ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) K_GATE(G_USBH, RCC_AHB6ENSETR, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) K_GATE(G_CRC1, RCC_AHB6ENSETR, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) K_MGATE(G_SDMMC2, RCC_AHB6ENSETR, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) K_MGATE(G_SDMMC1, RCC_AHB6ENSETR, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) K_MGATE(G_QSPI, RCC_AHB6ENSETR, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) K_MGATE(G_FMC, RCC_AHB6ENSETR, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) K_GATE(G_ETHMAC, RCC_AHB6ENSETR, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) K_GATE(G_ETHRX, RCC_AHB6ENSETR, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) K_GATE(G_ETHTX, RCC_AHB6ENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) K_GATE(G_ETHCK, RCC_AHB6ENSETR, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) K_MGATE(G_GPU, RCC_AHB6ENSETR, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) K_GATE(G_MDMA, RCC_AHB6ENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) K_GATE(G_ETHSTP, RCC_AHB6LPENSETR, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) M_SDMMC12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) M_SDMMC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) M_FMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) M_QSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) M_RNG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) M_RNG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) M_USBPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) M_USBO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) M_STGEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) M_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) M_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) M_SPI23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) M_SPI45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) M_SPI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) M_CEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) M_I2C12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) M_I2C35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) M_I2C46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) M_LPTIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) M_LPTIM23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) M_LPTIM45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) M_USART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) M_UART24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) M_UART35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) M_USART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) M_UART78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) M_SAI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) M_SAI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) M_SAI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) M_SAI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) M_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) M_FDCAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) M_ADC12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) M_ETHCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) M_CKPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) M_LAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static struct stm32_mmux ker_mux[M_LAST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) [_id] = {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) &(struct mux_cfg) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .reg_off = _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .shift = _shift,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .width = _width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .mux_flags = _mux_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .table = NULL,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .mmux = _mmux,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .ops = _ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) NULL, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) &ker_mux[_id], &clk_mmux_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) /* Kernel multi mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) K_MMUX(M_SPI45, RCC_SPI2S45CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) K_MMUX(M_I2C12, RCC_I2C12CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) K_MMUX(M_I2C35, RCC_I2C35CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) K_MMUX(M_LPTIM23, RCC_LPTIM23CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) K_MMUX(M_LPTIM45, RCC_LPTIM45CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) K_MMUX(M_UART24, RCC_UART24CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) K_MMUX(M_UART35, RCC_UART35CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) K_MMUX(M_UART78, RCC_UART78CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) K_MMUX(M_SAI1, RCC_SAI1CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) K_MMUX(M_ETHCK, RCC_ETHCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) K_MMUX(M_I2C46, RCC_I2C46CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* Kernel simple mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) K_MUX(M_RNG2, RCC_RNG2CKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) K_MUX(M_SDMMC3, RCC_SDMMC3CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) K_MUX(M_FMC, RCC_FMCCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) K_MUX(M_QSPI, RCC_QSPICKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) K_MUX(M_USBPHY, RCC_USBCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) K_MUX(M_USBO, RCC_USBCKSELR, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) K_MUX(M_SPDIF, RCC_SPDIFCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) K_MUX(M_SPI1, RCC_SPI2S1CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) K_MUX(M_CEC, RCC_CECCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) K_MUX(M_LPTIM1, RCC_LPTIM1CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) K_MUX(M_USART6, RCC_UART6CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) K_MUX(M_FDCAN, RCC_FDCANCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) K_MUX(M_SAI2, RCC_SAI2CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) K_MUX(M_SAI3, RCC_SAI3CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) K_MUX(M_SAI4, RCC_SAI4CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) K_MUX(M_ADC12, RCC_ADCCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) K_MUX(M_DSI, RCC_DSICKSELR, 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) K_MUX(M_CKPER, RCC_CPERCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) K_MUX(M_RNG1, RCC_RNG1CKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) K_MUX(M_STGEN, RCC_STGENCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) K_MUX(M_USART1, RCC_UART1CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) K_MUX(M_SPI6, RCC_SPI6CKSELR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static const struct clock_config stm32mp1_clock_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /* Oscillator divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) /* External / Internal Oscillators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* ck_csi is used by IO compensation and should be critical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) RCC_OCENSETR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* ref clock pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) 0, 2, CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) 0, 2, CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) 0, 2, CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /* PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* ODF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) _GATE(RCC_PLL1CR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) _GATE(RCC_PLL2CR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) _GATE(RCC_PLL2CR, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) _GATE(RCC_PLL2CR, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) _GATE(RCC_PLL3CR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) _GATE(RCC_PLL3CR, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) _GATE(RCC_PLL3CR, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) _GATE(RCC_PLL4CR, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) _GATE(RCC_PLL4CR, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) _GATE(RCC_PLL4CR, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* MUX system clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) RCC_CPERCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) COMPOSITE(CK_AXI, "ck_axi", axi_src, CLK_IS_CRITICAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) _NO_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) _MUX(RCC_ASSCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) _DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) COMPOSITE(CK_MCU, "ck_mcu", mcu_src, CLK_IS_CRITICAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) _NO_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) _MUX(RCC_MSSCKSELR, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) _DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /* Kernel Timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) STM32_CKTIM("ck1_tim", "pclk1", 0, RCC_APB1DIVR, RCC_TIMG1PRER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) STM32_CKTIM("ck2_tim", "pclk2", 0, RCC_APB2DIVR, RCC_TIMG2PRER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) STM32_TIM(TIM2_K, "tim2_k", "ck1_tim", RCC_APB1ENSETR, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) STM32_TIM(TIM3_K, "tim3_k", "ck1_tim", RCC_APB1ENSETR, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) STM32_TIM(TIM4_K, "tim4_k", "ck1_tim", RCC_APB1ENSETR, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) STM32_TIM(TIM5_K, "tim5_k", "ck1_tim", RCC_APB1ENSETR, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) STM32_TIM(TIM6_K, "tim6_k", "ck1_tim", RCC_APB1ENSETR, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) STM32_TIM(TIM7_K, "tim7_k", "ck1_tim", RCC_APB1ENSETR, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) STM32_TIM(TIM12_K, "tim12_k", "ck1_tim", RCC_APB1ENSETR, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) STM32_TIM(TIM13_K, "tim13_k", "ck1_tim", RCC_APB1ENSETR, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) STM32_TIM(TIM14_K, "tim14_k", "ck1_tim", RCC_APB1ENSETR, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) STM32_TIM(TIM1_K, "tim1_k", "ck2_tim", RCC_APB2ENSETR, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) STM32_TIM(TIM8_K, "tim8_k", "ck2_tim", RCC_APB2ENSETR, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) STM32_TIM(TIM15_K, "tim15_k", "ck2_tim", RCC_APB2ENSETR, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) STM32_TIM(TIM16_K, "tim16_k", "ck2_tim", RCC_APB2ENSETR, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) STM32_TIM(TIM17_K, "tim17_k", "ck2_tim", RCC_APB2ENSETR, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* Peripheral clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) PCLK(LPTIM1, "lptim1", "pclk1", 0, G_LPTIM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) PCLK(SPI2, "spi2", "pclk1", 0, G_SPI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) PCLK(SPI3, "spi3", "pclk1", 0, G_SPI3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) PCLK(USART2, "usart2", "pclk1", 0, G_USART2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) PCLK(USART3, "usart3", "pclk1", 0, G_USART3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) PCLK(UART4, "uart4", "pclk1", 0, G_UART4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) PCLK(UART7, "uart7", "pclk1", 0, G_UART7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) PCLK(UART8, "uart8", "pclk1", 0, G_UART8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) PCLK(I2C1, "i2c1", "pclk1", 0, G_I2C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) PCLK(I2C2, "i2c2", "pclk1", 0, G_I2C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) PCLK(I2C3, "i2c3", "pclk1", 0, G_I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) PCLK(I2C5, "i2c5", "pclk1", 0, G_I2C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) PCLK(SPDIF, "spdif", "pclk1", 0, G_SPDIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) PCLK(CEC, "cec", "pclk1", 0, G_CEC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) PCLK(DAC12, "dac12", "pclk1", 0, G_DAC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) PCLK(MDIO, "mdio", "pclk1", 0, G_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) PCLK(TIM1, "tim1", "pclk2", CLK_IGNORE_UNUSED, G_TIM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) PCLK(TIM8, "tim8", "pclk2", CLK_IGNORE_UNUSED, G_TIM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) PCLK(TIM15, "tim15", "pclk2", CLK_IGNORE_UNUSED, G_TIM15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) PCLK(TIM16, "tim16", "pclk2", CLK_IGNORE_UNUSED, G_TIM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) PCLK(TIM17, "tim17", "pclk2", CLK_IGNORE_UNUSED, G_TIM17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) PCLK(SPI1, "spi1", "pclk2", 0, G_SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) PCLK(SPI4, "spi4", "pclk2", 0, G_SPI4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) PCLK(SPI5, "spi5", "pclk2", 0, G_SPI5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) PCLK(USART6, "usart6", "pclk2", 0, G_USART6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) PCLK(SAI1, "sai1", "pclk2", 0, G_SAI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) PCLK(SAI2, "sai2", "pclk2", 0, G_SAI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) PCLK(SAI3, "sai3", "pclk2", 0, G_SAI3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) PCLK(DFSDM, "dfsdm", "pclk2", 0, G_DFSDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) PCLK(FDCAN, "fdcan", "pclk2", 0, G_FDCAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) PCLK(LPTIM2, "lptim2", "pclk3", 0, G_LPTIM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) PCLK(LPTIM3, "lptim3", "pclk3", 0, G_LPTIM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) PCLK(LPTIM4, "lptim4", "pclk3", 0, G_LPTIM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) PCLK(LPTIM5, "lptim5", "pclk3", 0, G_LPTIM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) PCLK(SAI4, "sai4", "pclk3", 0, G_SAI4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) PCLK(SYSCFG, "syscfg", "pclk3", 0, G_SYSCFG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) PCLK(VREF, "vref", "pclk3", 13, G_VREF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) PCLK(TMPSENS, "tmpsens", "pclk3", 0, G_TMPSENS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, G_PMBCTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) PCLK(IWDG2, "iwdg2", "pclk4", 0, G_IWDG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) PCLK(USBPHY, "usbphy", "pclk4", 0, G_USBPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) PCLK(STGENRO, "stgenro", "pclk4", 0, G_STGENRO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) PCLK(SPI6, "spi6", "pclk5", 0, G_SPI6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) PCLK(I2C4, "i2c4", "pclk5", 0, G_I2C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) PCLK(I2C6, "i2c6", "pclk5", 0, G_I2C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) CLK_IS_CRITICAL, G_RTCAPB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) PCLK(STGEN, "stgen", "pclk5", CLK_IGNORE_UNUSED, G_STGEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) PCLK(DMA1, "dma1", "ck_mcu", 0, G_DMA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) PCLK(DMA2, "dma2", "ck_mcu", 0, G_DMA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) PCLK(DMAMUX, "dmamux", "ck_mcu", 0, G_DMAMUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) PCLK(ADC12, "adc12", "ck_mcu", 0, G_ADC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) PCLK(USBO, "usbo", "ck_mcu", 0, G_USBO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) PCLK(SDMMC3, "sdmmc3", "ck_mcu", 0, G_SDMMC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) PCLK(DCMI, "dcmi", "ck_mcu", 0, G_DCMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) PCLK(CRYP2, "cryp2", "ck_mcu", 0, G_CRYP2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) PCLK(HASH2, "hash2", "ck_mcu", 0, G_HASH2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) PCLK(RNG2, "rng2", "ck_mcu", 0, G_RNG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) PCLK(CRC2, "crc2", "ck_mcu", 0, G_CRC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) PCLK(HSEM, "hsem", "ck_mcu", 0, G_HSEM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) PCLK(GPIOA, "gpioa", "ck_mcu", 0, G_GPIOA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) PCLK(GPIOB, "gpiob", "ck_mcu", 0, G_GPIOB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) PCLK(GPIOC, "gpioc", "ck_mcu", 0, G_GPIOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) PCLK(GPIOD, "gpiod", "ck_mcu", 0, G_GPIOD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) PCLK(GPIOE, "gpioe", "ck_mcu", 0, G_GPIOE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) PCLK(GPIOF, "gpiof", "ck_mcu", 0, G_GPIOF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) PCLK(GPIOG, "gpiog", "ck_mcu", 0, G_GPIOG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) PCLK(GPIOH, "gpioh", "ck_mcu", 0, G_GPIOH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) PCLK(GPIOI, "gpioi", "ck_mcu", 0, G_GPIOI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) PCLK(GPIOJ, "gpioj", "ck_mcu", 0, G_GPIOJ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) PCLK(GPIOK, "gpiok", "ck_mcu", 0, G_GPIOK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) PCLK(GPIOZ, "gpioz", "ck_axi", CLK_IGNORE_UNUSED, G_GPIOZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) PCLK(CRYP1, "cryp1", "ck_axi", CLK_IGNORE_UNUSED, G_CRYP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) PCLK(HASH1, "hash1", "ck_axi", CLK_IGNORE_UNUSED, G_HASH1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) PCLK(RNG1, "rng1", "ck_axi", 0, G_RNG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) PCLK(BKPSRAM, "bkpsram", "ck_axi", CLK_IGNORE_UNUSED, G_BKPSRAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) PCLK(GPU, "gpu", "ck_axi", 0, G_GPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) PCLK(SDMMC1, "sdmmc1", "ck_axi", 0, G_SDMMC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) PCLK(SDMMC2, "sdmmc2", "ck_axi", 0, G_SDMMC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* Kernel clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) KCLK(SDMMC2_K, "sdmmc2_k", sdmmc12_src, 0, G_SDMMC2, M_SDMMC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) KCLK(SDMMC3_K, "sdmmc3_k", sdmmc3_src, 0, G_SDMMC3, M_SDMMC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) KCLK(FMC_K, "fmc_k", fmc_src, 0, G_FMC, M_FMC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) KCLK(QSPI_K, "qspi_k", qspi_src, 0, G_QSPI, M_QSPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) KCLK(SPI3_K, "spi3_k", spi123_src, 0, G_SPI3, M_SPI23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) KCLK(SPI4_K, "spi4_k", spi45_src, 0, G_SPI4, M_SPI45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) KCLK(SPI5_K, "spi5_k", spi45_src, 0, G_SPI5, M_SPI45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) KCLK(SPI6_K, "spi6_k", spi6_src, 0, G_SPI6, M_SPI6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) KCLK(CEC_K, "cec_k", cec_src, 0, G_CEC, M_CEC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) KCLK(I2C1_K, "i2c1_k", i2c12_src, 0, G_I2C1, M_I2C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) KCLK(I2C2_K, "i2c2_k", i2c12_src, 0, G_I2C2, M_I2C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) KCLK(I2C3_K, "i2c3_k", i2c35_src, 0, G_I2C3, M_I2C35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) KCLK(I2C5_K, "i2c5_k", i2c35_src, 0, G_I2C5, M_I2C35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) KCLK(I2C4_K, "i2c4_k", i2c46_src, 0, G_I2C4, M_I2C46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) KCLK(I2C6_K, "i2c6_k", i2c46_src, 0, G_I2C6, M_I2C46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) KCLK(LPTIM1_K, "lptim1_k", lptim1_src, 0, G_LPTIM1, M_LPTIM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) KCLK(LPTIM2_K, "lptim2_k", lptim23_src, 0, G_LPTIM2, M_LPTIM23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) KCLK(LPTIM3_K, "lptim3_k", lptim23_src, 0, G_LPTIM3, M_LPTIM23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) KCLK(LPTIM4_K, "lptim4_k", lptim45_src, 0, G_LPTIM4, M_LPTIM45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) KCLK(LPTIM5_K, "lptim5_k", lptim45_src, 0, G_LPTIM5, M_LPTIM45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) KCLK(USART1_K, "usart1_k", usart1_src, 0, G_USART1, M_USART1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) KCLK(USART2_K, "usart2_k", usart234578_src, 0, G_USART2, M_UART24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) KCLK(USART3_K, "usart3_k", usart234578_src, 0, G_USART3, M_UART35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) KCLK(UART4_K, "uart4_k", usart234578_src, 0, G_UART4, M_UART24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) KCLK(UART5_K, "uart5_k", usart234578_src, 0, G_UART5, M_UART35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) KCLK(USART6_K, "uart6_k", usart6_src, 0, G_USART6, M_USART6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) KCLK(UART7_K, "uart7_k", usart234578_src, 0, G_UART7, M_UART78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) KCLK(UART8_K, "uart8_k", usart234578_src, 0, G_UART8, M_UART78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) /* Particulary Kernel Clocks (no mux or no gate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) MGATE_MP1(DSI_PX, "dsi_px", "pll4_q", CLK_SET_RATE_PARENT, G_DSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) MGATE_MP1(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, G_LTDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) _NO_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) _MMUX(M_ETHCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) /* RTC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) _GATE(RCC_BDCR, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) _MUX(RCC_BDCR, 16, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) _NO_DIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /* MCO clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) _GATE(RCC_MCO1CFGR, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) _MUX(RCC_MCO1CFGR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) _DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) _GATE(RCC_MCO2CFGR, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) _MUX(RCC_MCO2CFGR, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) /* Debug clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) RCC_DBGCFGR, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) _GATE(RCC_DBGCFGR, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) _NO_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) struct stm32_clock_match_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) const struct clock_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) unsigned int maxbinding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static struct stm32_clock_match_data stm32mp1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .cfg = stm32mp1_clock_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .num = ARRAY_SIZE(stm32mp1_clock_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .maxbinding = STM32MP1_LAST_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) static const struct of_device_id stm32mp1_match_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .compatible = "st,stm32mp1-rcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .data = &stm32mp1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static int stm32_register_hw_clk(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) void __iomem *base, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) const struct clock_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) struct clk_hw *hw = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) hws = clk_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (cfg->func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) pr_err("Unable to register %s\n", cfg->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (cfg->id != NO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) hws[cfg->id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static int stm32_rcc_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) const struct of_device_id *match_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) const struct stm32_clock_match_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) int err, n, max_binding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) match = of_match_node(match_data, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) pr_err("%s: match data not found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) max_binding = data->maxbinding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) clk_data = kzalloc(struct_size(clk_data, hws, max_binding),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) clk_data->num = max_binding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) hws = clk_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) for (n = 0; n < max_binding; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) hws[n] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) for (n = 0; n < data->num; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) err = stm32_register_hw_clk(NULL, clk_data, base, &rlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) &data->cfg[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) pr_err("%s: can't register %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) data->cfg[n].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) static void stm32mp1_rcc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) pr_err("%pOFn: unable to map resource", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) if (stm32_rcc_init(np, base, stm32mp1_match_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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