^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/stm32h7-clks.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Reset Clock Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RCC_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RCC_CFGR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RCC_D1CFGR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RCC_D2CFGR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RCC_D3CFGR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RCC_PLLCKSELR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RCC_PLLCFGR 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RCC_PLL1DIVR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RCC_PLL1FRACR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RCC_PLL2DIVR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RCC_PLL2FRACR 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RCC_PLL3DIVR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RCC_PLL3FRACR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RCC_D1CCIPR 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RCC_D2CCIP1R 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RCC_D2CCIP2R 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RCC_D3CCIPR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RCC_BDCR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RCC_CSR 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RCC_AHB3ENR 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RCC_AHB1ENR 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RCC_AHB2ENR 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RCC_AHB4ENR 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RCC_APB3ENR 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RCC_APB1LENR 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RCC_APB1HENR 0xEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RCC_APB2ENR 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RCC_APB4ENR 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static DEFINE_SPINLOCK(stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* System clock parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const char * const sys_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "hsi_ck", "csi_ck", "hse_ck", "pll1_p" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const char * const tracein_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "hsi_ck", "csi_ck", "hse_ck", "pll1_r" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const char * const per_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "hsi_ker", "csi_ker", "hse_ck", "disabled" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char * const pll_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "hsi_ck", "csi_ck", "hse_ck", "no clock" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const char * const sdmmc_src[] = { "pll1_q", "pll2_r" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const char * const dsi_src[] = { "ck_dsi_phy", "pll2_q" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const char * const qspi_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "hclk", "pll1_q", "pll2_r", "per_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const char * const fmc_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "hclk", "pll1_q", "pll2_r", "per_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Kernel clock parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const char * const swp_src[] = { "pclk1", "hsi_ker" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const char * const fdcan_src[] = { "hse_ck", "pll1_q", "pll2_q" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char * const dfsdm1_src[] = { "pclk2", "sys_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const char * const spdifrx_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "pll1_q", "pll2_r", "pll3_r", "hsi_ker" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char *spi_src1[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "pll1_q", "pll2_p", "pll3_p", NULL, "per_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const char * const spi_src2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "pclk2", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "hse_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const char * const spi_src3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "pclk4", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "hse_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char * const lptim_src1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "pclk1", "pll2_p", "pll3_r", "lse_ck", "lsi_ck", "per_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char * const lptim_src2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "pclk4", "pll2_p", "pll3_r", "lse_ck", "lsi_ck", "per_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char * const cec_src[] = {"lse_ck", "lsi_ck", "csi_ker_div122" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const char * const usbotg_src[] = {"pll1_q", "pll3_q", "rc48_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* i2c 1,2,3 src */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const char * const i2c_src1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "pclk1", "pll3_r", "hsi_ker", "csi_ker" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const i2c_src2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "pclk4", "pll3_r", "hsi_ker", "csi_ker" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const char * const rng_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "rc48_ck", "pll1_q", "lse_ck", "lsi_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* usart 1,6 src */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const usart_src1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "pclk2", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "lse_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* usart 2,3,4,5,7,8 src */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const char * const usart_src2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "pclk1", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "lse_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const char *sai_src[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "pll1_q", "pll2_p", "pll3_p", NULL, "per_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const char * const adc_src[] = { "pll2_p", "pll3_r", "per_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* lptim 2,3,4,5 src */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const char * const lpuart1_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "pclk3", "pll2_q", "pll3_q", "csi_ker", "lse_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char * const hrtim_src[] = { "tim2_ker", "d1cpre" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* RTC clock parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const char * const rtc_src[] = { "off", "lse_ck", "lsi_ck", "hse_1M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Micro-controller output clock parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const char * const mco_src1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "hsi_ck", "lse_ck", "hse_ck", "pll1_q", "rc48_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const char * const mco_src2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "sys_ck", "pll2_p", "hse_ck", "pll1_p", "csi_ck", "lsi_ck" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* LCD clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const char * const ltdc_src[] = {"pll3_r"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Gate clock with ready bit and backup domain management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct stm32_ready_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 bit_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define to_ready_gate_clk(_rgate) container_of(_rgate, struct stm32_ready_gate,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RGATE_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int ready_gate_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct stm32_ready_gate *rgate = to_ready_gate_clk(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int bit_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int timeout = RGATE_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (clk_gate_ops.is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clk_gate_ops.enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* We can't use readl_poll_timeout() because we can blocked if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * someone enables this clock before clocksource changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Only jiffies counter is available. Jiffies are incremented by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * interruptions and enable op does not allow to be interrupted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (bit_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } while (bit_status && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return bit_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void ready_gate_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct stm32_ready_gate *rgate = to_ready_gate_clk(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int bit_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int timeout = RGATE_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!clk_gate_ops.is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clk_gate_ops.disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (bit_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } while (bit_status && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct clk_ops ready_gate_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .enable = ready_gate_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .disable = ready_gate_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .is_enabled = clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct clk_hw *clk_register_ready_gate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void __iomem *reg, u8 bit_idx, u8 bit_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned long flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct stm32_ready_gate *rgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct clk_init_data init = { NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!rgate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) init.ops = &ready_gate_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rgate->bit_rdy = bit_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) rgate->gate.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rgate->gate.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rgate->gate.bit_idx = bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rgate->gate.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) hw = &rgate->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) kfree(rgate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct gate_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct muxdiv_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct composite_clk_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct gate_cfg *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct muxdiv_cfg *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct muxdiv_cfg *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const char * const *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct composite_clk_gcfg_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) const struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * General config definition of a composite clock (only clock diviser for rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct composite_clk_gcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct composite_clk_gcfg_t *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct composite_clk_gcfg_t *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct composite_clk_gcfg_t *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define M_CFG_MUX(_mux_ops, _mux_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .mux = &(struct composite_clk_gcfg_t) { _mux_flags, _mux_ops}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define M_CFG_DIV(_rate_ops, _rate_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .div = &(struct composite_clk_gcfg_t) {_rate_flags, _rate_ops}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define M_CFG_GATE(_gate_ops, _gate_flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .gate = &(struct composite_clk_gcfg_t) { _gate_flags, _gate_ops}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static struct clk_mux *_get_cmux(void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mux->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mux->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mux->mask = (1 << width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mux->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mux->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct clk_divider *_get_cdiv(void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct clk_divider *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) div = kzalloc(sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) div->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) div->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) div->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) div->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) div->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) gate->bit_idx = bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) gate->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) gate->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct composite_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct clk_hw *mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct clk_hw *div_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct clk_hw *gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) const struct clk_ops *mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) const struct clk_ops *div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) const struct clk_ops *gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void get_cfg_composite_div(const struct composite_clk_gcfg *gcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) const struct composite_clk_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct composite_cfg *composite, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct clk_mux *mux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct clk_divider *div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct clk_gate *gate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) const struct clk_ops *mux_ops, *div_ops, *gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct clk_hw *mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct clk_hw *div_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct clk_hw *gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mux_ops = div_ops = gate_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mux_hw = div_hw = gate_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (gcfg->mux && cfg->mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) mux = _get_cmux(base + cfg->mux->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cfg->mux->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) cfg->mux->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) gcfg->mux->flags, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!IS_ERR(mux)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mux_hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mux_ops = gcfg->mux->ops ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) gcfg->mux->ops : &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (gcfg->div && cfg->div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) div = _get_cdiv(base + cfg->div->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) cfg->div->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) cfg->div->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) gcfg->div->flags, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!IS_ERR(div)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) div_hw = &div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) div_ops = gcfg->div->ops ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) gcfg->div->ops : &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (gcfg->gate && cfg->gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) gate = _get_cgate(base + cfg->gate->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) cfg->gate->bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) gcfg->gate->flags, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!IS_ERR(gate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) gate_hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) gate_ops = gcfg->gate->ops ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gcfg->gate->ops : &clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) composite->mux_hw = mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) composite->mux_ops = mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) composite->div_hw = div_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) composite->div_ops = div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) composite->gate_hw = gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) composite->gate_ops = gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Kernel Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct timer_ker {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 dppre_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define to_timer_ker(_hw) container_of(_hw, struct timer_ker, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct timer_ker *clk_elem = to_timer_ker(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 timpre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 dppre_shift = clk_elem->dppre_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) timpre = (readl(base + RCC_CFGR) >> 15) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) prescaler = (readl(base + RCC_D2CFGR) >> dppre_shift) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mul = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (prescaler < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mul = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) else if (timpre && prescaler > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mul = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return parent_rate * mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct clk_ops timer_ker_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .recalc_rate = timer_ker_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static struct clk_hw *clk_register_stm32_timer_ker(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 dppre_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct timer_ker *element;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) element = kzalloc(sizeof(*element), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!element)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) init.ops = &timer_ker_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) element->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) element->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) element->dppre_shift = dppre_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) hw = &element->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) err = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) kfree(element);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct clk_div_table d1cpre_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { 4, 1 }, { 5, 1 }, { 6, 1 }, { 7, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { 8, 2 }, { 9, 4 }, { 10, 8 }, { 11, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { 12, 64 }, { 13, 128 }, { 14, 256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { 15, 512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct clk_div_table ppre_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static void register_core_and_bus_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* CORE AND BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) hws[SYS_D1CPRE] = clk_hw_register_divider_table(NULL, "d1cpre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "sys_ck", CLK_IGNORE_UNUSED, base + RCC_D1CFGR, 8, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) d1cpre_div_table, &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) CLK_IGNORE_UNUSED, base + RCC_D1CFGR, 0, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) d1cpre_div_table, &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* D1 DOMAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* * CPU Systick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) hws[CPU_SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "d1cpre", 0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* * APB3 peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) hws[PCLK3] = clk_hw_register_divider_table(NULL, "pclk3", "hclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) base + RCC_D1CFGR, 4, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ppre_div_table, &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* D2 DOMAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* * APB1 peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) hws[PCLK1] = clk_hw_register_divider_table(NULL, "pclk1", "hclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) base + RCC_D2CFGR, 4, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ppre_div_table, &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Timers prescaler clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) clk_register_stm32_timer_ker(NULL, "tim1_ker", "pclk1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 4, &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* * APB2 peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) hws[PCLK2] = clk_hw_register_divider_table(NULL, "pclk2", "hclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) base + RCC_D2CFGR, 8, 3, 0, ppre_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) clk_register_stm32_timer_ker(NULL, "tim2_ker", "pclk2", 0, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* D3 DOMAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* * APB4 peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) hws[PCLK4] = clk_hw_register_divider_table(NULL, "pclk4", "hclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) base + RCC_D3CFGR, 4, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ppre_div_table, &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* MUX clock configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct stm32_mux_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) const char * const *parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, _flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .parents = _parents,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .num_parents = ARRAY_SIZE(_parents),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .offset = _mux_offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .shift = _mux_shift,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .width = _mux_width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define M_MCLOC(_name, _parents, _mux_offset, _mux_shift, _mux_width)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, 0)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const struct stm32_mux_clk stm32_mclk[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) M_MCLOC("per_ck", per_src, RCC_D1CCIPR, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) M_MCLOC("pllsrc", pll_src, RCC_PLLCKSELR, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) M_MCLOC("sys_ck", sys_src, RCC_CFGR, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) M_MCLOC("tracein_ck", tracein_src, RCC_CFGR, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Oscillary clock configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct stm32_osc_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 gate_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 bit_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, _flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .parent = _parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .gate_offset = _gate_offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .bit_idx = _bit_idx,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .bit_rdy = _bit_rdy,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define OSC_CLK(_name, _parent, _gate_offset, _bit_idx, _bit_rdy)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const struct stm32_osc_clk stm32_oclk[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) OSC_CLKF("hsi_ck", "hsidiv", RCC_CR, 0, 2, CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) OSC_CLKF("hsi_ker", "hsidiv", RCC_CR, 1, 2, CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) OSC_CLKF("csi_ck", "clk-csi", RCC_CR, 7, 8, CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) OSC_CLKF("csi_ker", "clk-csi", RCC_CR, 9, 8, CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) OSC_CLKF("rc48_ck", "clk-rc48", RCC_CR, 12, 13, CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) OSC_CLKF("lsi_ck", "clk-lsi", RCC_CSR, 0, 1, CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* PLL configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct st32h7_pll_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u32 offset_divr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u8 bit_frac_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 offset_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u8 divm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct stm32_pll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) const struct st32h7_pll_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct st32h7_pll_cfg stm32h7_pll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .bit_idx = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .offset_divr = RCC_PLL1DIVR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .bit_frac_en = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .offset_frac = RCC_PLL1FRACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .divm = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct st32h7_pll_cfg stm32h7_pll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .bit_idx = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .offset_divr = RCC_PLL2DIVR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .bit_frac_en = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .offset_frac = RCC_PLL2FRACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .divm = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const struct st32h7_pll_cfg stm32h7_pll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .bit_idx = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .offset_divr = RCC_PLL3DIVR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .bit_frac_en = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .offset_frac = RCC_PLL3FRACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .divm = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const struct stm32_pll_data stm32_pll[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { "vco1", "pllsrc", CLK_IGNORE_UNUSED, &stm32h7_pll1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { "vco2", "pllsrc", 0, &stm32h7_pll2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { "vco3", "pllsrc", 0, &stm32h7_pll3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct stm32_fractional_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) void __iomem *mreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 mshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u8 mwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 mmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) void __iomem *nreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 nshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u8 nwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) void __iomem *freg_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 freg_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) void __iomem *freg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u8 fshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 fwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct stm32_pll_obj {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct stm32_fractional_divider div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct stm32_ready_gate rgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct clk_hw *_hw = &clk_elem->rgate.gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) __clk_hw_set_clk(_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return ready_gate_clk_ops.is_enabled(_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct clk_hw *_hw = &clk_elem->rgate.gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __clk_hw_set_clk(_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return ready_gate_clk_ops.enable(_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static void pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct clk_hw *_hw = &clk_elem->rgate.gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) __clk_hw_set_clk(_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ready_gate_clk_ops.disable(_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int pll_frac_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct stm32_fractional_divider *fd = &clk_elem->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return (readl(fd->freg_status) >> fd->freg_bit) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static unsigned long pll_read_frac(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct stm32_fractional_divider *fd = &clk_elem->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return (readl(fd->freg_value) >> fd->fshift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) GENMASK(fd->fwidth - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static unsigned long pll_fd_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct stm32_pll_obj *clk_elem = to_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct stm32_fractional_divider *fd = &clk_elem->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned long m, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u64 rate, rate1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) val = readl(fd->mreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mask = GENMASK(fd->mwidth - 1, 0) << fd->mshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) m = (val & mask) >> fd->mshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) val = readl(fd->nreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mask = GENMASK(fd->nwidth - 1, 0) << fd->nshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) n = ((val & mask) >> fd->nshift) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!n || !m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) rate = (u64)parent_rate * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) do_div(rate, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (pll_frac_is_enabled(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) val = pll_read_frac(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) rate1 = (u64)parent_rate * (u64)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) do_div(rate1, (m * 8191));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return rate + rate1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct clk_ops pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .enable = pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .disable = pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .is_enabled = pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .recalc_rate = pll_fd_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct clk_hw *clk_register_stm32_pll(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) const struct st32h7_pll_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct stm32_pll_obj *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct clk_init_data init = { NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct stm32_fractional_divider *div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct stm32_ready_gate *rgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) init.ops = &pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) init.parent_names = &parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) hw = &pll->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rgate = &pll->rgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) rgate->bit_rdy = cfg->bit_idx + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) rgate->gate.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) rgate->gate.reg = base + RCC_CR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) rgate->gate.bit_idx = cfg->bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) div = &pll->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) div->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) div->mreg = base + RCC_PLLCKSELR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) div->mshift = cfg->divm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) div->mwidth = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) div->nreg = base + cfg->offset_divr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) div->nshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) div->nwidth = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) div->freg_status = base + RCC_PLLCFGR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) div->freg_bit = cfg->bit_frac_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) div->freg_value = base + cfg->offset_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) div->fshift = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) div->fwidth = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) div->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* ODF CLOCKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static unsigned long odf_divider_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return clk_divider_ops.recalc_rate(hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static long odf_divider_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return clk_divider_ops.round_rate(hw, rate, prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int odf_divider_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct clk_hw *hwp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int pll_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) hwp = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) pll_status = pll_is_enabled(hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (pll_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pll_disable(hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (pll_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) pll_enable(hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const struct clk_ops odf_divider_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .recalc_rate = odf_divider_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .round_rate = odf_divider_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .set_rate = odf_divider_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static int odf_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct clk_hw *hwp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) int pll_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (clk_gate_ops.is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) hwp = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) pll_status = pll_is_enabled(hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (pll_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pll_disable(hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = clk_gate_ops.enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (pll_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) pll_enable(hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static void odf_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct clk_hw *hwp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int pll_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (!clk_gate_ops.is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) hwp = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pll_status = pll_is_enabled(hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (pll_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) pll_disable(hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) clk_gate_ops.disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (pll_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) pll_enable(hwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const struct clk_ops odf_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .enable = odf_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .disable = odf_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .is_enabled = clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static struct composite_clk_gcfg odf_clk_gcfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) M_CFG_DIV(&odf_divider_ops, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) M_CFG_GATE(&odf_gate_ops, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define M_ODF_F(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) _rate_shift, _rate_width, _flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .mux = NULL,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .div = &(struct muxdiv_cfg) {_rate_offset, _rate_shift, _rate_width},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .gate = &(struct gate_cfg) {_gate_offset, _bit_idx },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .parent_name = &(const char *) {_parent},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .num_parents = 1,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define M_ODF(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) _rate_shift, _rate_width)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) M_ODF_F(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) _rate_shift, _rate_width, 0)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const struct composite_clk_cfg stm32_odf[3][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) M_ODF_F("pll1_p", "vco1", RCC_PLLCFGR, 16, RCC_PLL1DIVR, 9, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) M_ODF_F("pll1_q", "vco1", RCC_PLLCFGR, 17, RCC_PLL1DIVR, 16, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) M_ODF_F("pll1_r", "vco1", RCC_PLLCFGR, 18, RCC_PLL1DIVR, 24, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) M_ODF("pll2_p", "vco2", RCC_PLLCFGR, 19, RCC_PLL2DIVR, 9, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) M_ODF("pll2_q", "vco2", RCC_PLLCFGR, 20, RCC_PLL2DIVR, 16, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) M_ODF("pll2_r", "vco2", RCC_PLLCFGR, 21, RCC_PLL2DIVR, 24, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) M_ODF("pll3_p", "vco3", RCC_PLLCFGR, 22, RCC_PLL3DIVR, 9, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) M_ODF("pll3_q", "vco3", RCC_PLLCFGR, 23, RCC_PLL3DIVR, 16, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) M_ODF("pll3_r", "vco3", RCC_PLLCFGR, 24, RCC_PLL3DIVR, 24, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* PERIF CLOCKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct pclk_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 gate_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define PER_CLKF(_gate_offset, _bit_idx, _name, _parent, _flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .gate_offset = _gate_offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .bit_idx = _bit_idx,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .parent = _parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define PER_CLK(_gate_offset, _bit_idx, _name, _parent)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PER_CLKF(_gate_offset, _bit_idx, _name, _parent, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const struct pclk_t pclk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PER_CLK(RCC_AHB3ENR, 31, "d1sram1", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PER_CLK(RCC_AHB3ENR, 30, "itcm", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PER_CLK(RCC_AHB3ENR, 29, "dtcm2", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PER_CLK(RCC_AHB3ENR, 28, "dtcm1", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PER_CLK(RCC_AHB3ENR, 8, "flitf", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PER_CLK(RCC_AHB3ENR, 5, "jpgdec", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PER_CLK(RCC_AHB3ENR, 4, "dma2d", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PER_CLK(RCC_AHB3ENR, 0, "mdma", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PER_CLK(RCC_AHB1ENR, 28, "usb2ulpi", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PER_CLK(RCC_AHB1ENR, 26, "usb1ulpi", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PER_CLK(RCC_AHB1ENR, 17, "eth1rx", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PER_CLK(RCC_AHB1ENR, 16, "eth1tx", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PER_CLK(RCC_AHB1ENR, 15, "eth1mac", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PER_CLK(RCC_AHB1ENR, 14, "art", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PER_CLK(RCC_AHB1ENR, 1, "dma2", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PER_CLK(RCC_AHB1ENR, 0, "dma1", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PER_CLK(RCC_AHB2ENR, 31, "d2sram3", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PER_CLK(RCC_AHB2ENR, 30, "d2sram2", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PER_CLK(RCC_AHB2ENR, 29, "d2sram1", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PER_CLK(RCC_AHB2ENR, 5, "hash", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PER_CLK(RCC_AHB2ENR, 4, "crypt", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PER_CLK(RCC_AHB2ENR, 0, "camitf", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PER_CLK(RCC_AHB4ENR, 28, "bkpram", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PER_CLK(RCC_AHB4ENR, 25, "hsem", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PER_CLK(RCC_AHB4ENR, 21, "bdma", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PER_CLK(RCC_AHB4ENR, 19, "crc", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PER_CLK(RCC_AHB4ENR, 10, "gpiok", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PER_CLK(RCC_AHB4ENR, 9, "gpioj", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PER_CLK(RCC_AHB4ENR, 8, "gpioi", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PER_CLK(RCC_AHB4ENR, 7, "gpioh", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PER_CLK(RCC_AHB4ENR, 6, "gpiog", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PER_CLK(RCC_AHB4ENR, 5, "gpiof", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PER_CLK(RCC_AHB4ENR, 4, "gpioe", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PER_CLK(RCC_AHB4ENR, 3, "gpiod", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PER_CLK(RCC_AHB4ENR, 2, "gpioc", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PER_CLK(RCC_AHB4ENR, 1, "gpiob", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PER_CLK(RCC_AHB4ENR, 0, "gpioa", "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PER_CLK(RCC_APB3ENR, 6, "wwdg1", "pclk3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PER_CLK(RCC_APB1LENR, 29, "dac12", "pclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PER_CLK(RCC_APB1LENR, 11, "wwdg2", "pclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PER_CLK(RCC_APB1LENR, 8, "tim14", "tim1_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PER_CLK(RCC_APB1LENR, 7, "tim13", "tim1_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PER_CLK(RCC_APB1LENR, 6, "tim12", "tim1_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PER_CLK(RCC_APB1LENR, 5, "tim7", "tim1_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PER_CLK(RCC_APB1LENR, 4, "tim6", "tim1_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PER_CLK(RCC_APB1LENR, 3, "tim5", "tim1_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PER_CLK(RCC_APB1LENR, 2, "tim4", "tim1_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PER_CLK(RCC_APB1LENR, 1, "tim3", "tim1_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PER_CLK(RCC_APB1LENR, 0, "tim2", "tim1_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PER_CLK(RCC_APB1HENR, 5, "mdios", "pclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PER_CLK(RCC_APB1HENR, 4, "opamp", "pclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PER_CLK(RCC_APB1HENR, 1, "crs", "pclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PER_CLK(RCC_APB2ENR, 18, "tim17", "tim2_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PER_CLK(RCC_APB2ENR, 17, "tim16", "tim2_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PER_CLK(RCC_APB2ENR, 16, "tim15", "tim2_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PER_CLK(RCC_APB2ENR, 1, "tim8", "tim2_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PER_CLK(RCC_APB2ENR, 0, "tim1", "tim2_ker"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PER_CLK(RCC_APB4ENR, 26, "tmpsens", "pclk4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PER_CLK(RCC_APB4ENR, 16, "rtcapb", "pclk4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PER_CLK(RCC_APB4ENR, 15, "vref", "pclk4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PER_CLK(RCC_APB4ENR, 14, "comp12", "pclk4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PER_CLK(RCC_APB4ENR, 1, "syscfg", "pclk4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* KERNEL CLOCKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define KER_CLKF(_gate_offset, _bit_idx,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) _mux_offset, _mux_shift, _mux_width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) _name, _parent_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .gate = &(struct gate_cfg) {_gate_offset, _bit_idx},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .mux = &(struct muxdiv_cfg) {_mux_offset, _mux_shift, _mux_width },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .parent_name = _parent_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .num_parents = ARRAY_SIZE(_parent_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define KER_CLK(_gate_offset, _bit_idx, _mux_offset, _mux_shift, _mux_width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) _name, _parent_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) KER_CLKF(_gate_offset, _bit_idx, _mux_offset, _mux_shift, _mux_width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) _name, _parent_name, 0)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define KER_CLKF_NOMUX(_gate_offset, _bit_idx,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) _name, _parent_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .gate = &(struct gate_cfg) {_gate_offset, _bit_idx},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .mux = NULL,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .parent_name = _parent_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .num_parents = 1,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static const struct composite_clk_cfg kclk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) KER_CLK(RCC_AHB3ENR, 16, RCC_D1CCIPR, 16, 1, "sdmmc1", sdmmc_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) KER_CLKF(RCC_AHB3ENR, 14, RCC_D1CCIPR, 4, 2, "quadspi", qspi_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) KER_CLKF(RCC_AHB3ENR, 12, RCC_D1CCIPR, 0, 2, "fmc", fmc_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) KER_CLK(RCC_AHB1ENR, 27, RCC_D2CCIP2R, 20, 2, "usb2otg", usbotg_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) KER_CLK(RCC_AHB1ENR, 25, RCC_D2CCIP2R, 20, 2, "usb1otg", usbotg_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) KER_CLK(RCC_AHB1ENR, 5, RCC_D3CCIPR, 16, 2, "adc12", adc_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) KER_CLK(RCC_AHB2ENR, 9, RCC_D1CCIPR, 16, 1, "sdmmc2", sdmmc_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) KER_CLK(RCC_AHB2ENR, 6, RCC_D2CCIP2R, 8, 2, "rng", rng_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) KER_CLK(RCC_AHB4ENR, 24, RCC_D3CCIPR, 16, 2, "adc3", adc_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) KER_CLKF(RCC_APB3ENR, 4, RCC_D1CCIPR, 8, 1, "dsi", dsi_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) KER_CLKF_NOMUX(RCC_APB3ENR, 3, "ltdc", ltdc_src, CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) KER_CLK(RCC_APB1LENR, 31, RCC_D2CCIP2R, 0, 3, "usart8", usart_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) KER_CLK(RCC_APB1LENR, 30, RCC_D2CCIP2R, 0, 3, "usart7", usart_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) KER_CLK(RCC_APB1LENR, 27, RCC_D2CCIP2R, 22, 2, "hdmicec", cec_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) KER_CLK(RCC_APB1LENR, 23, RCC_D2CCIP2R, 12, 2, "i2c3", i2c_src1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) KER_CLK(RCC_APB1LENR, 22, RCC_D2CCIP2R, 12, 2, "i2c2", i2c_src1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) KER_CLK(RCC_APB1LENR, 21, RCC_D2CCIP2R, 12, 2, "i2c1", i2c_src1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) KER_CLK(RCC_APB1LENR, 20, RCC_D2CCIP2R, 0, 3, "uart5", usart_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) KER_CLK(RCC_APB1LENR, 19, RCC_D2CCIP2R, 0, 3, "uart4", usart_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) KER_CLK(RCC_APB1LENR, 18, RCC_D2CCIP2R, 0, 3, "usart3", usart_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) KER_CLK(RCC_APB1LENR, 17, RCC_D2CCIP2R, 0, 3, "usart2", usart_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) KER_CLK(RCC_APB1LENR, 16, RCC_D2CCIP1R, 20, 2, "spdifrx", spdifrx_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) KER_CLK(RCC_APB1LENR, 15, RCC_D2CCIP1R, 16, 3, "spi3", spi_src1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) KER_CLK(RCC_APB1LENR, 14, RCC_D2CCIP1R, 16, 3, "spi2", spi_src1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) KER_CLK(RCC_APB1LENR, 9, RCC_D2CCIP2R, 28, 3, "lptim1", lptim_src1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) KER_CLK(RCC_APB1HENR, 8, RCC_D2CCIP1R, 28, 2, "fdcan", fdcan_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) KER_CLK(RCC_APB1HENR, 2, RCC_D2CCIP1R, 31, 1, "swp", swp_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) KER_CLK(RCC_APB2ENR, 29, RCC_CFGR, 14, 1, "hrtim", hrtim_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) KER_CLK(RCC_APB2ENR, 28, RCC_D2CCIP1R, 24, 1, "dfsdm1", dfsdm1_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) KER_CLKF(RCC_APB2ENR, 24, RCC_D2CCIP1R, 6, 3, "sai3", sai_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) KER_CLKF(RCC_APB2ENR, 23, RCC_D2CCIP1R, 6, 3, "sai2", sai_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) KER_CLKF(RCC_APB2ENR, 22, RCC_D2CCIP1R, 0, 3, "sai1", sai_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) KER_CLK(RCC_APB2ENR, 20, RCC_D2CCIP1R, 16, 3, "spi5", spi_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) KER_CLK(RCC_APB2ENR, 13, RCC_D2CCIP1R, 16, 3, "spi4", spi_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) KER_CLK(RCC_APB2ENR, 12, RCC_D2CCIP1R, 16, 3, "spi1", spi_src1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) KER_CLK(RCC_APB2ENR, 5, RCC_D2CCIP2R, 3, 3, "usart6", usart_src1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) KER_CLK(RCC_APB2ENR, 4, RCC_D2CCIP2R, 3, 3, "usart1", usart_src1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) KER_CLK(RCC_APB4ENR, 21, RCC_D3CCIPR, 24, 3, "sai4b", sai_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) KER_CLK(RCC_APB4ENR, 21, RCC_D3CCIPR, 21, 3, "sai4a", sai_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) KER_CLK(RCC_APB4ENR, 12, RCC_D3CCIPR, 13, 3, "lptim5", lptim_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) KER_CLK(RCC_APB4ENR, 11, RCC_D3CCIPR, 13, 3, "lptim4", lptim_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) KER_CLK(RCC_APB4ENR, 10, RCC_D3CCIPR, 13, 3, "lptim3", lptim_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) KER_CLK(RCC_APB4ENR, 9, RCC_D3CCIPR, 10, 3, "lptim2", lptim_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) KER_CLK(RCC_APB4ENR, 7, RCC_D3CCIPR, 8, 2, "i2c4", i2c_src2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) KER_CLK(RCC_APB4ENR, 5, RCC_D3CCIPR, 28, 3, "spi6", spi_src3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) KER_CLK(RCC_APB4ENR, 3, RCC_D3CCIPR, 0, 3, "lpuart1", lpuart1_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static struct composite_clk_gcfg kernel_clk_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) M_CFG_MUX(NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) M_CFG_GATE(NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* RTC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * RTC & LSE registers are protected against parasitic write access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * PWR_CR_DBP bit must be set to enable write access to RTC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* STM32_PWR_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define PWR_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* STM32_PWR_CR bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define PWR_CR_DBP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static struct composite_clk_gcfg rtc_clk_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) M_CFG_MUX(NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) M_CFG_GATE(NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static const struct composite_clk_cfg rtc_clk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) KER_CLK(RCC_BDCR, 15, RCC_BDCR, 8, 2, "rtc_ck", rtc_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Micro-controller output clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static struct composite_clk_gcfg mco_clk_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) M_CFG_MUX(NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) M_CFG_DIV(NULL, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define M_MCO_F(_name, _parents, _mux_offset, _mux_shift, _mux_width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) _rate_offset, _rate_shift, _rate_width,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) _flags)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .mux = &(struct muxdiv_cfg) {_mux_offset, _mux_shift, _mux_width },\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .div = &(struct muxdiv_cfg) {_rate_offset, _rate_shift, _rate_width},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .gate = NULL,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .parent_name = _parents,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .num_parents = ARRAY_SIZE(_parents),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .flags = _flags,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static const struct composite_clk_cfg mco_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) M_MCO_F("mco1", mco_src1, RCC_CFGR, 22, 4, RCC_CFGR, 18, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) M_MCO_F("mco2", mco_src2, RCC_CFGR, 29, 3, RCC_CFGR, 25, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static void __init stm32h7_rcc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct composite_cfg c_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) const char *hse_clk, *lse_clk, *i2s_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct regmap *pdrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) clk_data = kzalloc(struct_size(clk_data, hws, STM32H7_MAX_CLKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) clk_data->num = STM32H7_MAX_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) hws = clk_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) for (n = 0; n < STM32H7_MAX_CLKS; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) hws[n] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* get RCC base @ from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) pr_err("%pOFn: unable to map resource", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) goto err_free_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (IS_ERR(pdrm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) pr_warn("%s: Unable to get syscfg\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* In any case disable backup domain write protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * and will never be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * Needed by LSE & RTC clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) regmap_update_bits(pdrm, PWR_CR, PWR_CR_DBP, PWR_CR_DBP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* Put parent names from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) hse_clk = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) lse_clk = of_clk_get_parent_name(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) i2s_clk = of_clk_get_parent_name(np, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) sai_src[3] = i2s_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) spi_src1[3] = i2s_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Register Internal oscillators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) clk_hw_register_fixed_rate(NULL, "clk-hsi", NULL, 0, 64000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) clk_hw_register_fixed_rate(NULL, "clk-csi", NULL, 0, 4000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) clk_hw_register_fixed_rate(NULL, "clk-lsi", NULL, 0, 32000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) clk_hw_register_fixed_rate(NULL, "clk-rc48", NULL, 0, 48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* This clock is coming from outside. Frequencies unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) hws[CK_DSI_PHY] = clk_hw_register_fixed_rate(NULL, "ck_dsi_phy", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) hws[HSI_DIV] = clk_hw_register_divider(NULL, "hsidiv", "clk-hsi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) base + RCC_CR, 3, 2, CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) hws[HSE_1M] = clk_hw_register_divider(NULL, "hse_1M", "hse_ck", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) base + RCC_CFGR, 8, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* Mux system clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) for (n = 0; n < ARRAY_SIZE(stm32_mclk); n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) hws[MCLK_BANK + n] = clk_hw_register_mux(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) stm32_mclk[n].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) stm32_mclk[n].parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) stm32_mclk[n].num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) stm32_mclk[n].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) stm32_mclk[n].offset + base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) stm32_mclk[n].shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) stm32_mclk[n].width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) register_core_and_bus_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* Oscillary clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) for (n = 0; n < ARRAY_SIZE(stm32_oclk); n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) hws[OSC_BANK + n] = clk_register_ready_gate(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) stm32_oclk[n].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) stm32_oclk[n].parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) stm32_oclk[n].gate_offset + base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) stm32_oclk[n].bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) stm32_oclk[n].bit_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) stm32_oclk[n].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) hws[HSE_CK] = clk_register_ready_gate(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) "hse_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) hse_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) RCC_CR + base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) 16, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) hws[LSE_CK] = clk_register_ready_gate(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) "lse_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) lse_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) RCC_BDCR + base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) hws[CSI_KER_DIV122 + n] = clk_hw_register_fixed_factor(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) "csi_ker_div122", "csi_ker", 0, 1, 122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) for (n = 0; n < ARRAY_SIZE(stm32_pll); n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) int odf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Register the VCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) clk_register_stm32_pll(NULL, stm32_pll[n].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) stm32_pll[n].parent_name, stm32_pll[n].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) stm32_pll[n].cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* Register the 3 output dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) for (odf = 0; odf < 3; odf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) int idx = n * 3 + odf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) get_cfg_composite_div(&odf_clk_gcfg, &stm32_odf[n][odf],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) &c_cfg, &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) hws[ODF_BANK + idx] = clk_hw_register_composite(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) stm32_odf[n][odf].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) stm32_odf[n][odf].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) stm32_odf[n][odf].num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) c_cfg.mux_hw, c_cfg.mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) c_cfg.div_hw, c_cfg.div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) c_cfg.gate_hw, c_cfg.gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) stm32_odf[n][odf].flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* Peripheral clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) for (n = 0; n < ARRAY_SIZE(pclk); n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) hws[PERIF_BANK + n] = clk_hw_register_gate(NULL, pclk[n].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pclk[n].parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) pclk[n].flags, base + pclk[n].gate_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) pclk[n].bit_idx, pclk[n].flags, &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* Kernel clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) for (n = 0; n < ARRAY_SIZE(kclk); n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) get_cfg_composite_div(&kernel_clk_cfg, &kclk[n], &c_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) hws[KERN_BANK + n] = clk_hw_register_composite(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) kclk[n].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) kclk[n].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) kclk[n].num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) c_cfg.mux_hw, c_cfg.mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) c_cfg.div_hw, c_cfg.div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) c_cfg.gate_hw, c_cfg.gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) kclk[n].flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* RTC clock (default state is off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) clk_hw_register_fixed_rate(NULL, "off", NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) get_cfg_composite_div(&rtc_clk_cfg, &rtc_clk, &c_cfg, &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) hws[RTC_CK] = clk_hw_register_composite(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) rtc_clk.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) rtc_clk.parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) rtc_clk.num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) c_cfg.mux_hw, c_cfg.mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) c_cfg.div_hw, c_cfg.div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) c_cfg.gate_hw, c_cfg.gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) rtc_clk.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* Micro-controller clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) for (n = 0; n < ARRAY_SIZE(mco_clk); n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) get_cfg_composite_div(&mco_clk_cfg, &mco_clk[n], &c_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) &stm32rcc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) hws[MCO_BANK + n] = clk_hw_register_composite(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) mco_clk[n].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) mco_clk[n].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) mco_clk[n].num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) c_cfg.mux_hw, c_cfg.mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) c_cfg.div_hw, c_cfg.div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) c_cfg.gate_hw, c_cfg.gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) mco_clk[n].flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) err_free_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* The RCC node is a clock and reset controller, and these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * functionalities are supported by different drivers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * matches the same compatible strings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) CLK_OF_DECLARE_DRIVER(stm32h7_rcc, "st,stm32h743-rcc", stm32h7_rcc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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