^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Author: Daniel Thompson <daniel.thompson@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Inspired by clk-asm9260.c .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Include list of clocks wich are not derived from system clock (SYSCLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * The index of these clocks is the secondary index of DT bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <dt-bindings/clock/stm32fx-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STM32F4_RCC_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STM32F4_RCC_PLLCFGR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STM32F4_RCC_CFGR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STM32F4_RCC_AHB1ENR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STM32F4_RCC_AHB2ENR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STM32F4_RCC_AHB3ENR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STM32F4_RCC_APB1ENR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STM32F4_RCC_APB2ENR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STM32F4_RCC_BDCR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STM32F4_RCC_CSR 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STM32F4_RCC_PLLI2SCFGR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STM32F4_RCC_PLLSAICFGR 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STM32F4_RCC_DCKCFGR 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STM32F7_RCC_DCKCFGR2 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NONE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NO_IDX NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NO_MUX NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NO_GATE NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct stm32f4_gate_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { STM32F4_RCC_APB2ENR, 11, "sdmmc", "sdmux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { STM32F4_RCC_AHB2ENR, 1, "jpeg", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { STM32F4_RCC_APB1ENR, 10, "rtcapb", "apb1_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { STM32F4_RCC_APB1ENR, 13, "can3", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { STM32F4_RCC_APB2ENR, 11, "sdmmc1", "sdmux1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { STM32F4_RCC_APB2ENR, 30, "mdio", "apb2_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * have gate bits associated with them. Its combined hweight is 71.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define MAX_GATE_MAP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0x0000000000000001ull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x04777f33f6fec9ffull };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x0000000000000003ull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x0c777f33f6fec9ffull };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0x0000000000000003ull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x04f77f833e01c9ffull };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const u64 stm32f769_gate_map[MAX_GATE_MAP] = { 0x000000f37ef417ffull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0x0000000000000003ull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x44F77F833E01EDFFull };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const u64 *stm32f4_gate_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct clk_hw **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static DEFINE_SPINLOCK(stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct regmap *pdrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int stm32fx_end_primary_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * "Multiplier" device for APBx clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * mode, they also tap out the one of the low order state bits to run the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * timers. ST datasheets represent this feature as a (conditional) clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * multiplier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct clk_apb_mul {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct clk_apb_mul *am = to_clk_apb_mul(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return parent_rate * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct clk_apb_mul *am = to_clk_apb_mul(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned long mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mult = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long best_parent = rate / mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return *prate * mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * We must report success but we can do so unconditionally because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * clk_apb_mul_round_rate returns values that ensure this call is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * nop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const struct clk_ops clk_apb_mul_factor_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .round_rate = clk_apb_mul_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .set_rate = clk_apb_mul_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .recalc_rate = clk_apb_mul_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long flags, u8 bit_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct clk_apb_mul *am;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) am = kzalloc(sizeof(*am), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!am)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) am->bit_idx = bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) am->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) init.ops = &clk_apb_mul_factor_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) clk = clk_register(dev, &am->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) kfree(am);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PLL_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PLL_SAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct clk_div_table pll_divp_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const struct clk_div_table pll_divq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { 14, 14 }, { 15, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct clk_div_table pll_divr_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct stm32f4_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 bit_rdy_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 n_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct stm32f4_pll_post_div_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int pll_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u8 flag_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) const struct clk_div_table *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct stm32f4_vco_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) const char *vco_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u8 bit_rdy_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const struct stm32f4_vco_data vco_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { "vco", STM32F4_RCC_PLLCFGR, 24, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const struct clk_div_table post_divr_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define MAX_POST_DIV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct stm32f4_div_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 flag_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) const struct clk_div_table *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define MAX_PLL_DIV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { 16, 2, 0, pll_divp_table },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { 24, 4, 0, pll_divq_table },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { 28, 3, 0, pll_divr_table },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct stm32f4_pll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u8 pll_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u8 n_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) const char *div_name[MAX_PLL_DIV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { PLL, 192, { "pll", "pll48", NULL } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { PLL, 50, { "pll", "pll-q", "pll-r" } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int stm32f4_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return clk_gate_ops.is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define PLL_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int stm32f4_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct stm32f4_pll *pll = to_stm32f4_pll(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int bit_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int timeout = PLL_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (clk_gate_ops.is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clk_gate_ops.enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) } while (bit_status && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return bit_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static void stm32f4_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) clk_gate_ops.disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct stm32f4_pll *pll = to_stm32f4_pll(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned long n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) n = (readl(base + pll->offset) >> 6) & 0x1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return parent_rate * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct stm32f4_pll *pll = to_stm32f4_pll(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned long n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) n = rate / *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (n < pll->n_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) n = pll->n_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) else if (n > 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) n = 432;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return *prate * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct stm32f4_pll *pll = to_stm32f4_pll(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned long n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int pll_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pll_state = stm32f4_pll_is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (pll_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) stm32f4_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) n = rate / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val = readl(base + pll->offset) & ~(0x1ff << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) writel(val | ((n & 0x1ff) << 6), base + pll->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (pll_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) stm32f4_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static const struct clk_ops stm32f4_pll_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .enable = stm32f4_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .disable = stm32f4_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .is_enabled = stm32f4_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .recalc_rate = stm32f4_pll_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .round_rate = stm32f4_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .set_rate = stm32f4_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct stm32f4_pll_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct clk_divider div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct clk_hw *hw_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return clk_divider_ops.recalc_rate(hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return clk_divider_ops.round_rate(hw, rate, prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int pll_state, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct clk_divider *div = to_clk_divider(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (pll_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) stm32f4_pll_disable(pll_div->hw_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (pll_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) stm32f4_pll_enable(pll_div->hw_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const struct clk_ops stm32f4_pll_div_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .recalc_rate = stm32f4_pll_div_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .round_rate = stm32f4_pll_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .set_rate = stm32f4_pll_div_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static struct clk_hw *clk_register_pll_div(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u8 clk_divider_flags, const struct clk_div_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct clk_hw *pll_hw, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct stm32f4_pll_div *pll_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* allocate the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!pll_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) init.ops = &stm32f4_pll_div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* struct clk_divider assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pll_div->div.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pll_div->div.shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pll_div->div.width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) pll_div->div.flags = clk_divider_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pll_div->div.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pll_div->div.table = table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) pll_div->div.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) pll_div->hw_pll = pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* register the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) hw = &pll_div->div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) kfree(pll_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) const struct stm32f4_pll_data *data, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct stm32f4_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct clk_init_data init = { NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct clk_hw *pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) const struct stm32f4_vco_data *vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) vco = &vco_data[data->pll_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) init.name = vco->vco_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) init.ops = &stm32f4_pll_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) init.flags = CLK_SET_RATE_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) init.parent_names = &pllsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pll->gate.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) pll->gate.reg = base + STM32F4_RCC_CR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pll->gate.bit_idx = vco->bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) pll->gate.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pll->offset = vco->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pll->n_start = data->n_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pll->bit_rdy_idx = vco->bit_rdy_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) reg = base + pll->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pll_hw = &pll->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = clk_hw_register(NULL, pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) for (i = 0; i < MAX_PLL_DIV; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (data->div_name[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) clk_register_pll_div(data->div_name[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) vco->vco_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) div_data[i].shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) div_data[i].width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) div_data[i].flag_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) div_data[i].div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) pll_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * Converts the primary and secondary indices (as they appear in DT) to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * offset into our struct clock array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u64 table[MAX_GATE_MAP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (primary == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (WARN_ON(secondary >= stm32fx_end_primary_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return secondary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) memcpy(table, stm32f4_gate_map, sizeof(table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* only bits set in table can be used as indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 0 == (table[BIT_ULL_WORD(secondary)] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) BIT_ULL_MASK(secondary))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* mask out bits above our current index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) table[BIT_ULL_WORD(secondary)] &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static inline void disable_power_domain_write_protection(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (pdrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static inline void enable_power_domain_write_protection(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (pdrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static inline void sofware_reset_backup_domain(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) val = readl(base + STM32F4_RCC_BDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) writel(val | BIT(16), base + STM32F4_RCC_BDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct stm32_rgate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u8 bit_rdy_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define RGATE_TIMEOUT 50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int rgclk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct stm32_rgate *rgate = to_rgclk(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int bit_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) unsigned int timeout = RGATE_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (clk_gate_ops.is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) disable_power_domain_write_protection();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) clk_gate_ops.enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (bit_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) } while (bit_status && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) enable_power_domain_write_protection();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return bit_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static void rgclk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) clk_gate_ops.disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int rgclk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return clk_gate_ops.is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const struct clk_ops rgclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .enable = rgclk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .disable = rgclk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .is_enabled = rgclk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u8 clk_gate_flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct stm32_rgate *rgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct clk_init_data init = { NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!rgate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) init.ops = &rgclk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) rgate->bit_rdy_idx = bit_rdy_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) rgate->gate.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) rgate->gate.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) rgate->gate.bit_idx = bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) rgate->gate.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) hw = &rgate->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) kfree(rgate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static int cclk_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) disable_power_domain_write_protection();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret = clk_gate_ops.enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) enable_power_domain_write_protection();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void cclk_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) disable_power_domain_write_protection();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) clk_gate_ops.disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) enable_power_domain_write_protection();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static int cclk_gate_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return clk_gate_ops.is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static const struct clk_ops cclk_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .enable = cclk_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .disable = cclk_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .is_enabled = cclk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static u8 cclk_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return clk_mux_ops.get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) disable_power_domain_write_protection();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) sofware_reset_backup_domain();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret = clk_mux_ops.set_parent(hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) enable_power_domain_write_protection();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static const struct clk_ops cclk_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .get_parent = cclk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .set_parent = cclk_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) const char * const *parent_names, int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (!gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (!mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) gate->bit_idx = bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) gate->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) gate->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) mux->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) mux->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) mux->mask = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) mux->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) &mux->hw, &cclk_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) &gate->hw, &cclk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const struct clk_div_table ahb_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const struct clk_div_table apb_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static const char *rtc_parents[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) "no-clock", "lse", "lsi", "hse-rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static const char *pll_src = "pll-src";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const char *pllsrc_parent[2] = { "hsi", NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static const char *dsi_parent[2] = { NULL, "pll-r" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const char *lcd_parent[1] = { "pllsai-r-div" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static const char *i2s_parents[2] = { "plli2s-r", NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) "no-clock" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static const char *sdmux_parents[2] = { "pll48", "sys" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const char *hdmi_parents[2] = { "lse", "hsi_div488" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static const char *spdif_parent[1] = { "plli2s-p" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static const char * const dfsdm1_src[] = { "apb2_div", "sys" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static const char * const adsfdm1_parent[] = { "sai1_clk", "sai2_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct stm32_aux_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) int offset_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) int offset_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct stm32f4_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) const struct stm32f4_gate_data *gates_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) const u64 *gates_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) int gates_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) const struct stm32f4_pll_data *pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) const struct stm32_aux_clk *aux_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) int aux_clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int end_primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static const struct stm32_aux_clk stm32f429_aux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) NO_MUX, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) STM32F4_RCC_APB2ENR, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) STM32F4_RCC_CFGR, 23, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) STM32F4_RCC_DCKCFGR, 20, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) STM32F4_RCC_APB2ENR, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) STM32F4_RCC_DCKCFGR, 22, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) STM32F4_RCC_APB2ENR, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const struct stm32_aux_clk stm32f469_aux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) NO_MUX, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) STM32F4_RCC_APB2ENR, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) STM32F4_RCC_CFGR, 23, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) STM32F4_RCC_DCKCFGR, 20, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) STM32F4_RCC_APB2ENR, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) STM32F4_RCC_DCKCFGR, 22, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) STM32F4_RCC_APB2ENR, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) STM32F4_RCC_DCKCFGR, 27, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) STM32F4_RCC_DCKCFGR, 28, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) STM32F4_RCC_DCKCFGR, 29, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) STM32F4_RCC_APB2ENR, 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static const struct stm32_aux_clk stm32f746_aux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) NO_MUX, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) STM32F4_RCC_APB2ENR, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) STM32F4_RCC_CFGR, 23, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) STM32F4_RCC_DCKCFGR, 20, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) STM32F4_RCC_APB2ENR, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) STM32F4_RCC_DCKCFGR, 22, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) STM32F4_RCC_APB2ENR, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) STM32F7_RCC_DCKCFGR2, 27, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) STM32F7_RCC_DCKCFGR2, 28, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) CLK_HDMI_CEC, "hdmi-cec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) hdmi_parents, ARRAY_SIZE(hdmi_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) STM32F7_RCC_DCKCFGR2, 26, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) CLK_SPDIF, "spdif-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) spdif_parent, ARRAY_SIZE(spdif_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) STM32F7_RCC_DCKCFGR2, 22, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) STM32F4_RCC_APB2ENR, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) CLK_USART1, "usart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) uart_parents1, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) STM32F7_RCC_DCKCFGR2, 0, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) STM32F4_RCC_APB2ENR, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) CLK_USART2, "usart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) STM32F7_RCC_DCKCFGR2, 2, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) STM32F4_RCC_APB1ENR, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) CLK_USART3, "usart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) STM32F7_RCC_DCKCFGR2, 4, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) STM32F4_RCC_APB1ENR, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) CLK_UART4, "uart4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) STM32F7_RCC_DCKCFGR2, 6, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) STM32F4_RCC_APB1ENR, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) CLK_UART5, "uart5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) STM32F7_RCC_DCKCFGR2, 8, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) STM32F4_RCC_APB1ENR, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) CLK_USART6, "usart6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) uart_parents1, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) STM32F7_RCC_DCKCFGR2, 10, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) STM32F4_RCC_APB2ENR, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) CLK_UART7, "uart7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) STM32F7_RCC_DCKCFGR2, 12, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) STM32F4_RCC_APB1ENR, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) CLK_UART8, "uart8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) STM32F7_RCC_DCKCFGR2, 14, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) STM32F4_RCC_APB1ENR, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) CLK_I2C1, "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) i2c_parents, ARRAY_SIZE(i2c_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) STM32F7_RCC_DCKCFGR2, 16, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) STM32F4_RCC_APB1ENR, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) CLK_I2C2, "i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) i2c_parents, ARRAY_SIZE(i2c_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) STM32F7_RCC_DCKCFGR2, 18, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) STM32F4_RCC_APB1ENR, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) CLK_I2C3, "i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) i2c_parents, ARRAY_SIZE(i2c_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) STM32F7_RCC_DCKCFGR2, 20, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) STM32F4_RCC_APB1ENR, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) CLK_I2C4, "i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) i2c_parents, ARRAY_SIZE(i2c_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) STM32F7_RCC_DCKCFGR2, 22, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) STM32F4_RCC_APB1ENR, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) CLK_LPTIMER, "lptim1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) lptim_parent, ARRAY_SIZE(lptim_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) STM32F7_RCC_DCKCFGR2, 24, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) STM32F4_RCC_APB1ENR, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static const struct stm32_aux_clk stm32f769_aux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) NO_MUX, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) STM32F4_RCC_APB2ENR, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) STM32F4_RCC_CFGR, 23, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) STM32F4_RCC_DCKCFGR, 20, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) STM32F4_RCC_APB2ENR, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) STM32F4_RCC_DCKCFGR, 22, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) STM32F4_RCC_APB2ENR, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) STM32F7_RCC_DCKCFGR2, 27, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) NO_IDX, "sdmux1", sdmux_parents, ARRAY_SIZE(sdmux_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) STM32F7_RCC_DCKCFGR2, 28, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) NO_IDX, "sdmux2", sdmux_parents, ARRAY_SIZE(sdmux_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) STM32F7_RCC_DCKCFGR2, 29, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) CLK_HDMI_CEC, "hdmi-cec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) hdmi_parents, ARRAY_SIZE(hdmi_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) STM32F7_RCC_DCKCFGR2, 26, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) NO_GATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) CLK_SPDIF, "spdif-rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) spdif_parent, ARRAY_SIZE(spdif_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) STM32F7_RCC_DCKCFGR2, 22, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) STM32F4_RCC_APB2ENR, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) CLK_USART1, "usart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) uart_parents1, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) STM32F7_RCC_DCKCFGR2, 0, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) STM32F4_RCC_APB2ENR, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) CLK_USART2, "usart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) STM32F7_RCC_DCKCFGR2, 2, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) STM32F4_RCC_APB1ENR, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) CLK_USART3, "usart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) STM32F7_RCC_DCKCFGR2, 4, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) STM32F4_RCC_APB1ENR, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) CLK_UART4, "uart4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) STM32F7_RCC_DCKCFGR2, 6, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) STM32F4_RCC_APB1ENR, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) CLK_UART5, "uart5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) STM32F7_RCC_DCKCFGR2, 8, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) STM32F4_RCC_APB1ENR, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) CLK_USART6, "usart6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) uart_parents1, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) STM32F7_RCC_DCKCFGR2, 10, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) STM32F4_RCC_APB2ENR, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) CLK_UART7, "uart7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) STM32F7_RCC_DCKCFGR2, 12, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) STM32F4_RCC_APB1ENR, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) CLK_UART8, "uart8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) uart_parents2, ARRAY_SIZE(uart_parents1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) STM32F7_RCC_DCKCFGR2, 14, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) STM32F4_RCC_APB1ENR, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) CLK_I2C1, "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) i2c_parents, ARRAY_SIZE(i2c_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) STM32F7_RCC_DCKCFGR2, 16, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) STM32F4_RCC_APB1ENR, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) CLK_I2C2, "i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) i2c_parents, ARRAY_SIZE(i2c_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) STM32F7_RCC_DCKCFGR2, 18, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) STM32F4_RCC_APB1ENR, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) CLK_I2C3, "i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) i2c_parents, ARRAY_SIZE(i2c_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) STM32F7_RCC_DCKCFGR2, 20, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) STM32F4_RCC_APB1ENR, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) CLK_I2C4, "i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) i2c_parents, ARRAY_SIZE(i2c_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) STM32F7_RCC_DCKCFGR2, 22, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) STM32F4_RCC_APB1ENR, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) CLK_LPTIMER, "lptim1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) lptim_parent, ARRAY_SIZE(lptim_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) STM32F7_RCC_DCKCFGR2, 24, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) STM32F4_RCC_APB1ENR, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) CLK_F769_DSI, "dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) dsi_parent, ARRAY_SIZE(dsi_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) STM32F7_RCC_DCKCFGR2, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) STM32F4_RCC_APB2ENR, 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) CLK_DFSDM1, "dfsdm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) dfsdm1_src, ARRAY_SIZE(dfsdm1_src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) STM32F4_RCC_DCKCFGR, 25, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) STM32F4_RCC_APB2ENR, 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) CLK_ADFSDM1, "adfsdm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) adsfdm1_parent, ARRAY_SIZE(adsfdm1_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) STM32F4_RCC_DCKCFGR, 26, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) STM32F4_RCC_APB2ENR, 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static const struct stm32f4_clk_data stm32f429_clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .end_primary = END_PRIMARY_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .gates_data = stm32f429_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .gates_map = stm32f42xx_gate_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .gates_num = ARRAY_SIZE(stm32f429_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .pll_data = stm32f429_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .aux_clk = stm32f429_aux_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static const struct stm32f4_clk_data stm32f469_clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .end_primary = END_PRIMARY_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .gates_data = stm32f469_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .gates_map = stm32f46xx_gate_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .gates_num = ARRAY_SIZE(stm32f469_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .pll_data = stm32f469_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .aux_clk = stm32f469_aux_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .aux_clk_num = ARRAY_SIZE(stm32f469_aux_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static const struct stm32f4_clk_data stm32f746_clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .end_primary = END_PRIMARY_CLK_F7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .gates_data = stm32f746_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .gates_map = stm32f746_gate_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .gates_num = ARRAY_SIZE(stm32f746_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .pll_data = stm32f469_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .aux_clk = stm32f746_aux_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .aux_clk_num = ARRAY_SIZE(stm32f746_aux_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static const struct stm32f4_clk_data stm32f769_clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .end_primary = END_PRIMARY_CLK_F7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .gates_data = stm32f769_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .gates_map = stm32f769_gate_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .gates_num = ARRAY_SIZE(stm32f769_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .pll_data = stm32f469_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .aux_clk = stm32f769_aux_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .aux_clk_num = ARRAY_SIZE(stm32f769_aux_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static const struct of_device_id stm32f4_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .compatible = "st,stm32f42xx-rcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .data = &stm32f429_clk_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .compatible = "st,stm32f469-rcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .data = &stm32f469_clk_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .compatible = "st,stm32f746-rcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .data = &stm32f746_clk_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .compatible = "st,stm32f769-rcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .data = &stm32f769_clk_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static struct clk_hw *stm32_register_aux_clk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) const char * const *parent_names, int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) int offset_mux, u8 shift, u8 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) int offset_gate, u8 bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) unsigned long flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) struct clk_gate *gate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct clk_mux *mux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (offset_gate != NO_GATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (!gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) gate->reg = base + offset_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) gate->bit_idx = bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) gate->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) gate->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) gate_hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) gate_ops = &clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (offset_mux != NO_MUX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (!mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) mux->reg = base + offset_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) mux->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) mux->mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) mux->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) mux_hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) mux_ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (mux_hw == NULL && gate_hw == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) mux_hw, mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) gate_hw, gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static void __init stm32f4_rcc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) const char *hse_clk, *i2s_in_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) const struct stm32f4_clk_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) unsigned long pllm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) struct clk_hw *pll_src_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) pr_err("%pOFn: unable to map resource\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (IS_ERR(pdrm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) pdrm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) pr_warn("%s: Unable to get syscfg\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) match = of_match_node(stm32f4_of_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (WARN_ON(!match))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) stm32fx_end_primary_clk = data->end_primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) sizeof(*clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (!clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) stm32f4_gate_map = data->gates_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) hse_clk = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) dsi_parent[0] = hse_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) pllsrc_parent[1] = hse_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) i2s_in_clk = of_clk_get_parent_name(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) i2s_parents[1] = i2s_in_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) sai_parents[2] = i2s_in_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (of_device_is_compatible(np, "st,stm32f769-rcc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) base + STM32F4_RCC_APB2ENR, 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) CLK_IGNORE_UNUSED, &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) dsi_parent[0] = pll_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) sai_parents[3] = pll_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) NULL, 0, 16000000, 160000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) pll_src_hw = clk_hw_register_mux(NULL, pll_src, pllsrc_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) ARRAY_SIZE(pllsrc_parent), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) base + STM32F4_RCC_PLLCFGR, 22, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) clk_hw_register_fixed_factor(NULL, "vco_in", pll_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) 0, 1, pllm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) &data->pll_data[1], &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) &data->pll_data[2], &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) for (n = 0; n < MAX_POST_DIV; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) const struct stm32f4_pll_post_div_data *post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) post_div = &post_div_data[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) hw = clk_register_pll_div(post_div->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) post_div->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) post_div->flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) base + post_div->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) post_div->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) post_div->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) post_div->flag_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) post_div->div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) clks[post_div->pll_idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (post_div->idx != NO_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) clks[post_div->idx] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) sys_parents[1] = hse_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) clks[CLK_SYSCLK] = clk_hw_register_mux_table(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) clk_register_divider_table(NULL, "ahb_div", "sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) 4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) clk_register_divider_table(NULL, "apb1_div", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) 10, 3, 0, apb_div_table, &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) CLK_SET_RATE_PARENT, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) clk_register_divider_table(NULL, "apb2_div", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) 13, 3, 0, apb_div_table, &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) CLK_SET_RATE_PARENT, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) 0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) for (n = 0; n < data->gates_num; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) const struct stm32f4_gate_data *gd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) unsigned int secondary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) gd = &data->gates_data[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) gd->bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) clks[idx] = clk_hw_register_gate(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) NULL, gd->name, gd->parent_name, gd->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if (IS_ERR(clks[idx])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) pr_err("%pOF: Unable to register leaf clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) np, gd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (IS_ERR(clks[CLK_LSI])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) pr_err("Unable to register lsi clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (IS_ERR(clks[CLK_LSE])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) pr_err("Unable to register lse clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) 0, base + STM32F4_RCC_CFGR, 16, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (IS_ERR(clks[CLK_HSE_RTC])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) pr_err("Unable to register hse-rtc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (IS_ERR(clks[CLK_RTC])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) pr_err("Unable to register rtc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) for (n = 0; n < data->aux_clk_num; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) const struct stm32_aux_clk *aux_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) aux_clk = &data->aux_clk[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) hw = stm32_register_aux_clk(aux_clk->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) aux_clk->parent_names, aux_clk->num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) aux_clk->offset_mux, aux_clk->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) aux_clk->mask, aux_clk->offset_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) aux_clk->bit_idx, aux_clk->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) &stm32f4_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) pr_warn("Unable to register %s clk\n", aux_clk->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (aux_clk->idx != NO_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) clks[aux_clk->idx] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (of_device_is_compatible(np, "st,stm32f746-rcc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) 1, 488);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) clks[CLK_PLL_SRC] = pll_src_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) kfree(clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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