Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Microchip Sparx5 SoC Clock driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2019 Microchip Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Lars Povlsen <lars.povlsen@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <dt-bindings/clock/microchip,sparx5.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PLL_DIV		GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PLL_PRE_DIV	GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PLL_ROT_DIR	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PLL_ROT_SEL	GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PLL_ROT_ENA	BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PLL_CLK_ENA	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MAX_SEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MAX_PRE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static const u8 sel_rates[MAX_SEL] = { 0, 2*8, 2*4, 2*2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static const char *clk_names[N_CLOCKS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	"core", "ddr", "cpu2", "arm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	"aux1", "aux2", "aux3", "aux4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	"synce",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct s5_hw_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct s5_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct s5_hw_clk s5_hw[N_CLOCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct s5_pll_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	bool rot_ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u8 rot_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u8 rot_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u8 pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define to_s5_pll(hw) container_of(hw, struct s5_hw_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static unsigned long s5_calc_freq(unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				  const struct s5_pll_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned long rate = parent_rate / conf->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (conf->rot_ena) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		int sign = conf->rot_dir ? -1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		int divb = divt + sign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		rate = mult_frac(rate, divt, divb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		rate = roundup(rate, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void s5_search_fractional(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				 unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 				 int div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 				 struct s5_pll_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct s5_pll_conf best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ulong cur_offset, best_offset = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int d, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	memset(conf, 0, sizeof(*conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	conf->div = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	conf->rot_ena = 1;	/* Fractional rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	for (d = 0; best_offset > 0 && d <= 1 ; d++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		conf->rot_dir = !!d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		for (i = 0; best_offset > 0 && i < MAX_PRE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			conf->pre_div = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			for (j = 1; best_offset > 0 && j < MAX_SEL; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				conf->rot_sel = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				conf->freq = s5_calc_freq(parent_rate, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 				cur_offset = abs(rate - conf->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 				if (cur_offset < best_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 					best_offset = cur_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 					best = *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* Best match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	*conf = best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static unsigned long s5_calc_params(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				    unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				    struct s5_pll_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (parent_rate % rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		struct s5_pll_conf alt1, alt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		div = DIV_ROUND_CLOSEST_ULL(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		s5_search_fractional(rate, parent_rate, div, &alt1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		/* Straight match? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		if (alt1.freq == rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			*conf = alt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			/* Try without rounding divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			div = parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			if (div != alt1.div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				s5_search_fractional(rate, parent_rate, div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 						     &alt2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				/* Select the better match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				if (abs(rate - alt1.freq) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				    abs(rate - alt2.freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					*conf = alt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 					*conf = alt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		/* Straight fit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		memset(conf, 0, sizeof(*conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		conf->div = parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return conf->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int s5_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct s5_hw_clk *pll = to_s5_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 val = readl(pll->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	val |= PLL_CLK_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	writel(val, pll->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void s5_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct s5_hw_clk *pll = to_s5_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32 val = readl(pll->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	val &= ~PLL_CLK_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	writel(val, pll->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int s5_pll_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			   unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			   unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct s5_hw_clk *pll = to_s5_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct s5_pll_conf conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	unsigned long eff_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	eff_rate = s5_calc_params(rate, parent_rate, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (eff_rate != rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	val = readl(pll->reg) & PLL_CLK_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	val |= FIELD_PREP(PLL_DIV, conf.div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (conf.rot_ena) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		val |= PLL_ROT_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		val |= FIELD_PREP(PLL_ROT_SEL, conf.rot_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		val |= FIELD_PREP(PLL_PRE_DIV, conf.pre_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (conf.rot_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			val |= PLL_ROT_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	writel(val, pll->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static unsigned long s5_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 					unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct s5_hw_clk *pll = to_s5_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct s5_pll_conf conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	val = readl(pll->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (val & PLL_CLK_ENA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		conf.div     = FIELD_GET(PLL_DIV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		conf.pre_div = FIELD_GET(PLL_PRE_DIV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		conf.rot_ena = FIELD_GET(PLL_ROT_ENA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		conf.rot_dir = FIELD_GET(PLL_ROT_DIR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		conf.rot_sel = FIELD_GET(PLL_ROT_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		conf.freq = s5_calc_freq(parent_rate, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		conf.freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return conf.freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static long s5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			      unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct s5_pll_conf conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return s5_calc_params(rate, *parent_rate, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct clk_ops s5_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.enable		= s5_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.disable	= s5_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.set_rate	= s5_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.round_rate	= s5_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.recalc_rate	= s5_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct clk_hw *s5_clk_hw_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct s5_clk_data *s5_clk = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (idx >= N_CLOCKS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return &s5_clk->s5_hw[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int s5_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct s5_clk_data *s5_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct clk_parent_data pdata = { .index = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.ops = &s5_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.parent_data = &pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	s5_clk = devm_kzalloc(dev, sizeof(*s5_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (!s5_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	s5_clk->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (IS_ERR(s5_clk->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return PTR_ERR(s5_clk->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	for (i = 0; i < N_CLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		struct s5_hw_clk *s5_hw = &s5_clk->s5_hw[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		init.name = clk_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		s5_hw->reg = s5_clk->base + (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		s5_hw->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		ret = devm_clk_hw_register(dev, &s5_hw->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			dev_err(dev, "failed to register %s clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 				init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return devm_of_clk_add_hw_provider(dev, s5_clk_hw_get, s5_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct of_device_id s5_clk_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	{ .compatible = "microchip,sparx5-dpll", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_DEVICE_TABLE(of, s5_clk_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct platform_driver s5_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.probe  = s5_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.name = "sparx5-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.of_match_table = s5_clk_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) builtin_platform_driver(s5_clk_driver);