^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * clk-si5351.h: Silicon Laboratories Si5351A/B/C I2C Clock Generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Rabeeh Khoury <rabeeh@solid-run.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _CLK_SI5351_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _CLK_SI5351_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SI5351_BUS_BASE_ADDR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SI5351_PLL_VCO_MIN 600000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SI5351_PLL_VCO_MAX 900000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SI5351_MULTISYNTH_MIN_FREQ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SI5351_MULTISYNTH_DIVBY4_FREQ 150000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SI5351_MULTISYNTH_MAX_FREQ 160000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SI5351_CLKOUT_MIN_FREQ 8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SI5351_PLL_A_MIN 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SI5351_PLL_A_MAX 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SI5351_PLL_C_MAX 1048575
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SI5351_MULTISYNTH_A_MIN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SI5351_MULTISYNTH_A_MAX 1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SI5351_MULTISYNTH67_A_MAX 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SI5351_MULTISYNTH_C_MAX 1048575
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SI5351_MULTISYNTH_P1_MAX ((1<<18)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SI5351_MULTISYNTH_P2_MAX ((1<<20)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SI5351_MULTISYNTH_P3_MAX ((1<<20)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SI5351_DEVICE_STATUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SI5351_INTERRUPT_STATUS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SI5351_INTERRUPT_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SI5351_STATUS_SYS_INIT (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SI5351_STATUS_LOL_B (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SI5351_STATUS_LOL_A (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SI5351_STATUS_LOS (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SI5351_OUTPUT_ENABLE_CTRL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SI5351_OEB_PIN_ENABLE_CTRL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SI5351_PLL_INPUT_SOURCE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SI5351_CLKIN_DIV_MASK (3<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SI5351_CLKIN_DIV_1 (0<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SI5351_CLKIN_DIV_2 (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SI5351_CLKIN_DIV_4 (2<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SI5351_CLKIN_DIV_8 (3<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SI5351_PLLB_SOURCE (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SI5351_PLLA_SOURCE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SI5351_CLK0_CTRL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SI5351_CLK1_CTRL 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SI5351_CLK2_CTRL 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SI5351_CLK3_CTRL 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SI5351_CLK4_CTRL 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SI5351_CLK5_CTRL 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SI5351_CLK6_CTRL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SI5351_CLK7_CTRL 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SI5351_CLK_POWERDOWN (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SI5351_CLK_INTEGER_MODE (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SI5351_CLK_PLL_SELECT (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SI5351_CLK_INVERT (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SI5351_CLK_INPUT_MASK (3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SI5351_CLK_INPUT_XTAL (0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SI5351_CLK_INPUT_CLKIN (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SI5351_CLK3_0_DISABLE_STATE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SI5351_CLK7_4_DISABLE_STATE 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SI5351_CLK_DISABLE_STATE_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SI5351_CLK_DISABLE_STATE_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SI5351_CLK_DISABLE_STATE_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SI5351_CLK_DISABLE_STATE_FLOAT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SI5351_CLK_DISABLE_STATE_NEVER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SI5351_PARAMETERS_LENGTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SI5351_PLLA_PARAMETERS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SI5351_PLLB_PARAMETERS 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SI5351_CLK0_PARAMETERS 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SI5351_CLK1_PARAMETERS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SI5351_CLK2_PARAMETERS 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SI5351_CLK3_PARAMETERS 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SI5351_CLK4_PARAMETERS 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SI5351_CLK5_PARAMETERS 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SI5351_CLK6_PARAMETERS 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SI5351_CLK7_PARAMETERS 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SI5351_CLK6_7_OUTPUT_DIVIDER 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SI5351_OUTPUT_CLK_DIV_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SI5351_OUTPUT_CLK_DIV6_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SI5351_OUTPUT_CLK_DIV_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SI5351_OUTPUT_CLK_DIV_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SI5351_OUTPUT_CLK_DIV_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SI5351_OUTPUT_CLK_DIV_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SI5351_OUTPUT_CLK_DIV_16 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SI5351_OUTPUT_CLK_DIV_32 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SI5351_OUTPUT_CLK_DIV_64 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SI5351_OUTPUT_CLK_DIV_128 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SI5351_OUTPUT_CLK_DIVBY4 (3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SI5351_SSC_PARAM0 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SI5351_SSC_PARAM1 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SI5351_SSC_PARAM2 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SI5351_SSC_PARAM3 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SI5351_SSC_PARAM4 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SI5351_SSC_PARAM5 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SI5351_SSC_PARAM6 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SI5351_SSC_PARAM7 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SI5351_SSC_PARAM8 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SI5351_SSC_PARAM9 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SI5351_SSC_PARAM10 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SI5351_SSC_PARAM11 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SI5351_SSC_PARAM12 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SI5351_VXCO_PARAMETERS_LOW 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SI5351_VXCO_PARAMETERS_MID 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SI5351_VXCO_PARAMETERS_HIGH 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SI5351_CLK0_PHASE_OFFSET 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SI5351_CLK1_PHASE_OFFSET 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SI5351_CLK2_PHASE_OFFSET 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SI5351_CLK3_PHASE_OFFSET 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SI5351_CLK4_PHASE_OFFSET 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SI5351_CLK5_PHASE_OFFSET 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SI5351_PLL_RESET 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SI5351_PLL_RESET_B (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SI5351_PLL_RESET_A (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SI5351_CRYSTAL_LOAD 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SI5351_CRYSTAL_LOAD_MASK (3<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SI5351_CRYSTAL_LOAD_6PF (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SI5351_CRYSTAL_LOAD_8PF (2<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SI5351_CRYSTAL_LOAD_10PF (3<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SI5351_FANOUT_ENABLE 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SI5351_CLKIN_ENABLE (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SI5351_XTAL_ENABLE (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SI5351_MULTISYNTH_ENABLE (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * enum si5351_variant - SiLabs Si5351 chip variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) enum si5351_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SI5351_VARIANT_A = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SI5351_VARIANT_A3 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SI5351_VARIANT_B = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SI5351_VARIANT_C = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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