^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Rabeeh Khoury <rabeeh@solid-run.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * [1] "Si5351A/B/C Data Sheet"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * [2] "Manually Generating an Si5351 Register Map"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * https://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rational.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_data/si5351.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "clk-si5351.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct si5351_driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct si5351_parameters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct si5351_hw_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct si5351_driver_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct si5351_parameters params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned char num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct si5351_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum si5351_variant variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *pxtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const char *pxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk_hw xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct clk *pclkin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const char *pclkin_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk_hw clkin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct si5351_hw_data pll[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct si5351_hw_data *msynth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct si5351_hw_data *clkout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) size_t num_clkout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const char * const si5351_input_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "xtal", "clkin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const char * const si5351_pll_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "si5351_plla", "si5351_pllb", "si5351_vxco"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const char * const si5351_msynth_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const char * const si5351_clkout_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Si5351 i2c regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = regmap_read(drvdata->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_err(&drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "unable to read from reg%02x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return (u8)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline int si5351_bulk_read(struct si5351_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 reg, u8 count, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return regmap_bulk_read(drvdata->regmap, reg, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline int si5351_reg_write(struct si5351_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return regmap_write(drvdata->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline int si5351_bulk_write(struct si5351_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 reg, u8 count, const u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return regmap_raw_write(drvdata->regmap, reg, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline int si5351_set_bits(struct si5351_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return regmap_update_bits(drvdata->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline u8 si5351_msynth_params_address(int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (num > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return SI5351_CLK6_PARAMETERS + (num - 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void si5351_read_parameters(struct si5351_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 reg, struct si5351_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 buf[SI5351_PARAMETERS_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case SI5351_CLK6_PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case SI5351_CLK7_PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) buf[0] = si5351_reg_read(drvdata, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) params->p1 = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) params->p2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) params->p3 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) params->valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void si5351_write_parameters(struct si5351_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 reg, struct si5351_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 buf[SI5351_PARAMETERS_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case SI5351_CLK6_PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case SI5351_CLK7_PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) buf[0] = params->p1 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) si5351_reg_write(drvdata, reg, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) buf[1] = params->p3 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* save rdiv and divby4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) buf[4] = params->p1 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) buf[5] = ((params->p3 & 0xf0000) >> 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ((params->p2 & 0xf0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) buf[7] = params->p2 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case SI5351_DEVICE_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case SI5351_INTERRUPT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case SI5351_PLL_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* reserved registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (reg >= 4 && reg <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (reg >= 10 && reg <= 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (reg >= 173 && reg <= 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (reg >= 178 && reg <= 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (reg == SI5351_DEVICE_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct regmap_config si5351_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .max_register = 187,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .writeable_reg = si5351_regmap_is_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .volatile_reg = si5351_regmap_is_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Si5351 xtal clock input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int si5351_xtal_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct si5351_driver_data *drvdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) container_of(hw, struct si5351_driver_data, xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void si5351_xtal_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct si5351_driver_data *drvdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) container_of(hw, struct si5351_driver_data, xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SI5351_XTAL_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct clk_ops si5351_xtal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .prepare = si5351_xtal_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .unprepare = si5351_xtal_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Si5351 clkin clock input (Si5351C only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int si5351_clkin_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct si5351_driver_data *drvdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) container_of(hw, struct si5351_driver_data, clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void si5351_clkin_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct si5351_driver_data *drvdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) container_of(hw, struct si5351_driver_data, clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SI5351_CLKIN_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * CMOS clock source constraints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * The input frequency range of the PLL is 10Mhz to 40MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * If CLKIN is >40MHz, the input divider must be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct si5351_driver_data *drvdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) container_of(hw, struct si5351_driver_data, clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned char idiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (parent_rate > 160000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) idiv = SI5351_CLKIN_DIV_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) rate /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else if (parent_rate > 80000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) idiv = SI5351_CLKIN_DIV_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) rate /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } else if (parent_rate > 40000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) idiv = SI5351_CLKIN_DIV_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) idiv = SI5351_CLKIN_DIV_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SI5351_CLKIN_DIV_MASK, idiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __func__, (1 << (idiv >> 6)), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct clk_ops si5351_clkin_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .prepare = si5351_clkin_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .unprepare = si5351_clkin_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .recalc_rate = si5351_clkin_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Si5351 vxco clock input (Si5351B only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int si5351_vxco_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void si5351_vxco_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned long parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct clk_ops si5351_vxco_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .prepare = si5351_vxco_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .unprepare = si5351_vxco_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .recalc_rate = si5351_vxco_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .set_rate = si5351_vxco_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Si5351 pll a/b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Feedback Multisynth Divider Equations [2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * fVCO = fIN * (a + b/c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Feedback Multisynth Register Equations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * (3) MSNx_P3[19:0] = c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Using (4) on (1) yields:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int _si5351_pll_reparent(struct si5351_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int num, enum si5351_pll_src parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (parent == SI5351_PLL_SRC_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (num > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (drvdata->variant != SI5351_VARIANT_C &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) parent != SI5351_PLL_SRC_XTAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static unsigned char si5351_pll_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return (val & mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int si5351_pll_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (hwdata->drvdata->variant != SI5351_VARIANT_C &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (index > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return _si5351_pll_reparent(hwdata->drvdata, hwdata->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) (index == 0) ? SI5351_PLL_SRC_XTAL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SI5351_PLL_SRC_CLKIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) SI5351_PLLB_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!hwdata->params.valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (hwdata->params.p3 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) rate = hwdata->params.p1 * hwdata->params.p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rate += 512 * hwdata->params.p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) rate += hwdata->params.p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) rate *= parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) do_div(rate, 128 * hwdata->params.p3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_dbg(&hwdata->drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) __func__, clk_hw_get_name(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) parent_rate, (unsigned long)rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return (unsigned long)rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long rfrac, denom, a, b, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long long lltmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (rate < SI5351_PLL_VCO_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) rate = SI5351_PLL_VCO_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (rate > SI5351_PLL_VCO_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) rate = SI5351_PLL_VCO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* determine integer part of feedback equation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) a = rate / *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (a < SI5351_PLL_A_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) rate = *parent_rate * SI5351_PLL_A_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (a > SI5351_PLL_A_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rate = *parent_rate * SI5351_PLL_A_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* find best approximation for b/c = fVCO mod fIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) denom = 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) lltmp = rate % (*parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) lltmp *= denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) do_div(lltmp, *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rfrac = (unsigned long)lltmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) c = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (rfrac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) rational_best_approximation(rfrac, denom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* calculate parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) hwdata->params.p3 = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) hwdata->params.p2 = (128 * b) % c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) hwdata->params.p1 = 128 * a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hwdata->params.p1 += (128 * b / c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) hwdata->params.p1 -= 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* recalculate rate by fIN * (a + b/c) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) lltmp = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) lltmp *= b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) do_div(lltmp, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rate = (unsigned long)lltmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rate += *parent_rate * a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_dbg(&hwdata->drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) __func__, clk_hw_get_name(hw), a, b, c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) *parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) SI5351_PLLB_PARAMETERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* write multisynth parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* plla/pllb ctrl is in clk6/clk7 ctrl registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SI5351_CLK_INTEGER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Do a pll soft reset on the affected pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) hwdata->num == 0 ? SI5351_PLL_RESET_A :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) SI5351_PLL_RESET_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_dbg(&hwdata->drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) __func__, clk_hw_get_name(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct clk_ops si5351_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .set_parent = si5351_pll_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .get_parent = si5351_pll_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .recalc_rate = si5351_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .round_rate = si5351_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .set_rate = si5351_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Si5351 multisync divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * for fOUT <= 150 MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * fOUT = (fIN * (a + b/c)) / CLKOUTDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * fIN = fVCO0, fVCO1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Output Clock Multisynth Register Equations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * MSx_P3[19:0] = c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * MS[6,7] are integer (P1) divide only, P1 = divide value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * P2 and P3 are not applicable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * for 150MHz < fOUT <= 160MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int num, enum si5351_multisynth_src parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (parent == SI5351_MULTISYNTH_SRC_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (num > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) SI5351_CLK_PLL_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static unsigned char si5351_msynth_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) SI5351_MULTISYNTH_SRC_VCO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 reg = si5351_msynth_params_address(hwdata->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned long long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned long m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!hwdata->params.valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * multisync6-7: fOUT = fIN / P1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (hwdata->num > 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) m = hwdata->params.p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) } else if (hwdata->params.p3 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) m = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rate *= 128 * hwdata->params.p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) m = hwdata->params.p1 * hwdata->params.p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) m += hwdata->params.p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) m += 512 * hwdata->params.p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (m == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) do_div(rate, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_dbg(&hwdata->drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) __func__, clk_hw_get_name(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) m, parent_rate, (unsigned long)rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return (unsigned long)rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned long long lltmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned long a, b, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int divby4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* multisync6-7 can only handle freqencies < 150MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) rate = SI5351_MULTISYNTH67_MAX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* multisync frequency is 1MHz .. 160MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (rate > SI5351_MULTISYNTH_MAX_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) rate = SI5351_MULTISYNTH_MAX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (rate < SI5351_MULTISYNTH_MIN_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) rate = SI5351_MULTISYNTH_MIN_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) divby4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) divby4 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* multisync can set pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * find largest integer divider for max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * vco frequency and given target rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (divby4 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) lltmp = SI5351_PLL_VCO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) do_div(lltmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) a = (unsigned long)lltmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) a = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) c = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *parent_rate = a * rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) } else if (hwdata->num >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* determine the closest integer divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) a = DIV_ROUND_CLOSEST(*parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (a < SI5351_MULTISYNTH_A_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) a = SI5351_MULTISYNTH_A_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (a > SI5351_MULTISYNTH67_A_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) a = SI5351_MULTISYNTH67_A_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) c = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned long rfrac, denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* disable divby4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (divby4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) rate = SI5351_MULTISYNTH_DIVBY4_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) divby4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* determine integer part of divider equation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) a = *parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (a < SI5351_MULTISYNTH_A_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) a = SI5351_MULTISYNTH_A_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (a > SI5351_MULTISYNTH_A_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) a = SI5351_MULTISYNTH_A_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* find best approximation for b/c = fVCO mod fOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) denom = 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) lltmp = (*parent_rate) % rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) lltmp *= denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) do_div(lltmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) rfrac = (unsigned long)lltmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) c = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (rfrac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) rational_best_approximation(rfrac, denom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) &b, &c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* recalculate rate by fOUT = fIN / (a + b/c) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) lltmp = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) lltmp *= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) do_div(lltmp, a * c + b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) rate = (unsigned long)lltmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* calculate parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (divby4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) hwdata->params.p3 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) hwdata->params.p2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) hwdata->params.p1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) } else if (hwdata->num >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) hwdata->params.p3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) hwdata->params.p2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) hwdata->params.p1 = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) hwdata->params.p3 = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) hwdata->params.p2 = (128 * b) % c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) hwdata->params.p1 = 128 * a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) hwdata->params.p1 += (128 * b / c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) hwdata->params.p1 -= 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_dbg(&hwdata->drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) __func__, clk_hw_get_name(hw), a, b, c, divby4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) *parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u8 reg = si5351_msynth_params_address(hwdata->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int divby4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* write multisynth parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) divby4 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* enable/disable integer mode and divby4 on multisynth0-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (hwdata->num < 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) si5351_set_bits(hwdata->drvdata, reg + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) SI5351_OUTPUT_CLK_DIVBY4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) SI5351_CLK_INTEGER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev_dbg(&hwdata->drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) __func__, clk_hw_get_name(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) divby4, parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct clk_ops si5351_msynth_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .set_parent = si5351_msynth_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .get_parent = si5351_msynth_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .recalc_rate = si5351_msynth_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .round_rate = si5351_msynth_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .set_rate = si5351_msynth_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * Si5351 clkout divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int num, enum si5351_clkout_src parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (num > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) switch (parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case SI5351_CLKOUT_SRC_MSYNTH_N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) val = SI5351_CLK_INPUT_MULTISYNTH_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case SI5351_CLKOUT_SRC_MSYNTH_0_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* clk0/clk4 can only connect to its own multisync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (num == 0 || num == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) val = SI5351_CLK_INPUT_MULTISYNTH_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) val = SI5351_CLK_INPUT_MULTISYNTH_0_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case SI5351_CLKOUT_SRC_XTAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) val = SI5351_CLK_INPUT_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) case SI5351_CLKOUT_SRC_CLKIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (drvdata->variant != SI5351_VARIANT_C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) val = SI5351_CLK_INPUT_CLKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SI5351_CLK_INPUT_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int _si5351_clkout_set_drive_strength(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct si5351_driver_data *drvdata, int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) enum si5351_drive_strength drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (num > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) switch (drive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) case SI5351_DRIVE_2MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) mask = SI5351_CLK_DRIVE_STRENGTH_2MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case SI5351_DRIVE_4MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mask = SI5351_CLK_DRIVE_STRENGTH_4MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case SI5351_DRIVE_6MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) mask = SI5351_CLK_DRIVE_STRENGTH_6MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case SI5351_DRIVE_8MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) mask = SI5351_CLK_DRIVE_STRENGTH_8MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) SI5351_CLK_DRIVE_STRENGTH_MASK, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int _si5351_clkout_set_disable_state(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct si5351_driver_data *drvdata, int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) enum si5351_disable_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) SI5351_CLK7_4_DISABLE_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (num > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case SI5351_DISABLE_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) val = SI5351_CLK_DISABLE_STATE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case SI5351_DISABLE_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) val = SI5351_CLK_DISABLE_STATE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case SI5351_DISABLE_FLOATING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) val = SI5351_CLK_DISABLE_STATE_FLOAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case SI5351_DISABLE_NEVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) val = SI5351_CLK_DISABLE_STATE_NEVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) si5351_set_bits(drvdata, reg, mask, val << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) switch (val & SI5351_CLK_INPUT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case SI5351_CLK_INPUT_XTAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case SI5351_CLK_INPUT_CLKIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return; /* pll not used, no need to reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) si5351_reg_write(drvdata, SI5351_PLL_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) SI5351_PLL_RESET_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) __func__, clk_hw_get_name(&drvdata->clkout[num].hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) (val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int si5351_clkout_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct si5351_platform_data *pdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) hwdata->drvdata->client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) SI5351_CLK_POWERDOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * Do a pll soft reset on the parent pll -- needed to get a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * deterministic phase relationship between the output clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (pdata->clkout[hwdata->num].pll_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) (1 << hwdata->num), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void si5351_clkout_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) (1 << hwdata->num), (1 << hwdata->num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static u8 si5351_clkout_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) int index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) switch (val & SI5351_CLK_INPUT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case SI5351_CLK_INPUT_MULTISYNTH_N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case SI5351_CLK_INPUT_MULTISYNTH_0_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) case SI5351_CLK_INPUT_XTAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) index = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case SI5351_CLK_INPUT_CLKIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) index = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) parent = SI5351_CLKOUT_SRC_MSYNTH_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) parent = SI5351_CLKOUT_SRC_MSYNTH_0_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) parent = SI5351_CLKOUT_SRC_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) parent = SI5351_CLKOUT_SRC_CLKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned char rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (hwdata->num <= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) reg = si5351_msynth_params_address(hwdata->num) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) rdiv = si5351_reg_read(hwdata->drvdata, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (hwdata->num == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) rdiv &= SI5351_OUTPUT_CLK_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return parent_rate >> rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) unsigned char rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* clkout6/7 can only handle output freqencies < 150MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) rate = SI5351_CLKOUT67_MAX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* clkout freqency is 8kHz - 160MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (rate > SI5351_CLKOUT_MAX_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) rate = SI5351_CLKOUT_MAX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (rate < SI5351_CLKOUT_MIN_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) rate = SI5351_CLKOUT_MIN_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* request frequency if multisync master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* use r divider for frequencies below 1MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) rdiv = SI5351_OUTPUT_CLK_DIV_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) rdiv < SI5351_OUTPUT_CLK_DIV_128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) rdiv += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) *parent_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) unsigned long new_rate, new_err, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* round to closed rdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) rdiv = SI5351_OUTPUT_CLK_DIV_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) new_rate = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) err = abs(new_rate - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) new_rate >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) new_err = abs(new_rate - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) rdiv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) err = new_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) rate = *parent_rate >> rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev_dbg(&hwdata->drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) __func__, clk_hw_get_name(hw), (1 << rdiv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) *parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct si5351_hw_data *hwdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) container_of(hw, struct si5351_hw_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) unsigned long new_rate, new_err, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) unsigned char rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* round to closed rdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) rdiv = SI5351_OUTPUT_CLK_DIV_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) new_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) err = abs(new_rate - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) new_rate >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) new_err = abs(new_rate - rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) rdiv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) err = new_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* write output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) switch (hwdata->num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) SI5351_OUTPUT_CLK6_DIV_MASK, rdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) SI5351_OUTPUT_CLK_DIV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) si5351_set_bits(hwdata->drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) si5351_msynth_params_address(hwdata->num) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) SI5351_OUTPUT_CLK_DIV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* powerup clkout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) SI5351_CLK_POWERDOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) dev_dbg(&hwdata->drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) __func__, clk_hw_get_name(hw), (1 << rdiv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static const struct clk_ops si5351_clkout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .prepare = si5351_clkout_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .unprepare = si5351_clkout_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .set_parent = si5351_clkout_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .get_parent = si5351_clkout_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .recalc_rate = si5351_clkout_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .round_rate = si5351_clkout_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .set_rate = si5351_clkout_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * Si5351 i2c probe and DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static const struct of_device_id si5351_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) { .compatible = "silabs,si5351a-msop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .data = (void *)SI5351_VARIANT_A3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) MODULE_DEVICE_TABLE(of, si5351_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static int si5351_dt_parse(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) enum si5351_variant variant)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct device_node *child, *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct si5351_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) int num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (np == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * property silabs,pll-source : <num src>, [<..>]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * allow to selectively set pll source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (num >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) "invalid pll %d on pll-source prop\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) p = of_prop_next_u32(prop, p, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "missing pll-source for pll %d\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (variant != SI5351_VARIANT_C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "invalid parent %d for pll %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) val, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) "invalid parent %d for pll %d\n", val, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* per clkout properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (of_property_read_u32(child, "reg", &num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_err(&client->dev, "missing reg property of %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (num >= 8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) (variant == SI5351_VARIANT_A3 && num >= 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_err(&client->dev, "invalid clkout %d\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (!of_property_read_u32(child, "silabs,multisynth-source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) pdata->clkout[num].multisynth_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) SI5351_MULTISYNTH_SRC_VCO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) pdata->clkout[num].multisynth_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) SI5351_MULTISYNTH_SRC_VCO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) "invalid parent %d for multisynth %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) val, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (!of_property_read_u32(child, "silabs,clock-source", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) pdata->clkout[num].clkout_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) SI5351_CLKOUT_SRC_MSYNTH_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) pdata->clkout[num].clkout_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) SI5351_CLKOUT_SRC_MSYNTH_0_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) pdata->clkout[num].clkout_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) SI5351_CLKOUT_SRC_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (variant != SI5351_VARIANT_C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) "invalid parent %d for clkout %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) val, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) pdata->clkout[num].clkout_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) SI5351_CLKOUT_SRC_CLKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) "invalid parent %d for clkout %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) val, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (!of_property_read_u32(child, "silabs,drive-strength",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) case SI5351_DRIVE_2MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case SI5351_DRIVE_4MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) case SI5351_DRIVE_6MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) case SI5351_DRIVE_8MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) pdata->clkout[num].drive = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) "invalid drive strength %d for clkout %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) val, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!of_property_read_u32(child, "silabs,disable-state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pdata->clkout[num].disable_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) SI5351_DISABLE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) pdata->clkout[num].disable_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) SI5351_DISABLE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) pdata->clkout[num].disable_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) SI5351_DISABLE_FLOATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) pdata->clkout[num].disable_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) SI5351_DISABLE_NEVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) "invalid disable state %d for clkout %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) val, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!of_property_read_u32(child, "clock-frequency", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) pdata->clkout[num].rate = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) pdata->clkout[num].pll_master =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) of_property_read_bool(child, "silabs,pll-master");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) pdata->clkout[num].pll_reset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) of_property_read_bool(child, "silabs,pll-reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) client->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct si5351_driver_data *drvdata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (idx >= drvdata->num_clkout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return &drvdata->clkout[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static int si5351_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) enum si5351_variant variant = (enum si5351_variant)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct si5351_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct si5351_driver_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) const char *parent_names[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) u8 num_parents, num_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) int ret, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ret = si5351_dt_parse(client, variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) i2c_set_clientdata(client, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) drvdata->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) drvdata->variant = variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) drvdata->pxtal = devm_clk_get(&client->dev, "xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) drvdata->pclkin = devm_clk_get(&client->dev, "clkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * VARIANT_C can have CLKIN instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (IS_ERR(drvdata->pxtal) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) dev_err(&client->dev, "missing parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (IS_ERR(drvdata->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dev_err(&client->dev, "failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return PTR_ERR(drvdata->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* Ensure pll select is on XTAL for Si5351A/B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (drvdata->variant != SI5351_VARIANT_C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* setup clock configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) for (n = 0; n < 2; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) "failed to reparent pll %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) n, pdata->pll_src[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) for (n = 0; n < 8; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ret = _si5351_msynth_reparent(drvdata, n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) pdata->clkout[n].multisynth_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) "failed to reparent multisynth %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) n, pdata->clkout[n].multisynth_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ret = _si5351_clkout_reparent(drvdata, n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) pdata->clkout[n].clkout_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) "failed to reparent clkout %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) n, pdata->clkout[n].clkout_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ret = _si5351_clkout_set_drive_strength(drvdata, n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) pdata->clkout[n].drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) "failed set drive strength of clkout%d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) n, pdata->clkout[n].drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ret = _si5351_clkout_set_disable_state(drvdata, n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) pdata->clkout[n].disable_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) "failed set disable state of clkout%d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) n, pdata->clkout[n].disable_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* register xtal input clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) init.name = si5351_input_names[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) init.ops = &si5351_xtal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (!IS_ERR(drvdata->pxtal)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) drvdata->pxtal_name = __clk_get_name(drvdata->pxtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) init.parent_names = &drvdata->pxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) drvdata->xtal.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ret = devm_clk_hw_register(&client->dev, &drvdata->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) dev_err(&client->dev, "unable to register %s\n", init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* register clkin input clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (drvdata->variant == SI5351_VARIANT_C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) init.name = si5351_input_names[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) init.ops = &si5351_clkin_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (!IS_ERR(drvdata->pclkin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) drvdata->pclkin_name = __clk_get_name(drvdata->pclkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) init.parent_names = &drvdata->pclkin_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) drvdata->clkin.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ret = devm_clk_hw_register(&client->dev, &drvdata->clkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dev_err(&client->dev, "unable to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* Si5351C allows to mux either xtal or clkin to PLL input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) parent_names[0] = si5351_input_names[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) parent_names[1] = si5351_input_names[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* register PLLA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) drvdata->pll[0].num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) drvdata->pll[0].drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) drvdata->pll[0].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) init.name = si5351_pll_names[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) init.ops = &si5351_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) dev_err(&client->dev, "unable to register %s\n", init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* register PLLB or VXCO (Si5351B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) drvdata->pll[1].num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) drvdata->pll[1].drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) drvdata->pll[1].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (drvdata->variant == SI5351_VARIANT_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) init.name = si5351_pll_names[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) init.ops = &si5351_vxco_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) init.name = si5351_pll_names[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) init.ops = &si5351_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_err(&client->dev, "unable to register %s\n", init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* register clk multisync and clk out divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) parent_names[0] = si5351_pll_names[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (drvdata->variant == SI5351_VARIANT_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) parent_names[1] = si5351_pll_names[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) parent_names[1] = si5351_pll_names[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) drvdata->msynth = devm_kcalloc(&client->dev, num_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) sizeof(*drvdata->msynth), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) drvdata->clkout = devm_kcalloc(&client->dev, num_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) sizeof(*drvdata->clkout), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) drvdata->num_clkout = num_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) for (n = 0; n < num_clocks; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) drvdata->msynth[n].num = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) drvdata->msynth[n].drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) drvdata->msynth[n].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) init.name = si5351_msynth_names[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) init.ops = &si5351_msynth_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (pdata->clkout[n].pll_master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) init.flags |= CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) init.num_parents = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ret = devm_clk_hw_register(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) &drvdata->msynth[n].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dev_err(&client->dev, "unable to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) parent_names[2] = si5351_input_names[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) parent_names[3] = si5351_input_names[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) for (n = 0; n < num_clocks; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) parent_names[0] = si5351_msynth_names[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) parent_names[1] = (n < 4) ? si5351_msynth_names[0] :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) si5351_msynth_names[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) drvdata->clkout[n].num = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) drvdata->clkout[n].drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) drvdata->clkout[n].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) init.name = si5351_clkout_names[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) init.ops = &si5351_clkout_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) init.flags |= CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ret = devm_clk_hw_register(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) &drvdata->clkout[n].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) dev_err(&client->dev, "unable to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* set initial clkout rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (pdata->clkout[n].rate != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) ret = clk_set_rate(drvdata->clkout[n].hw.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) pdata->clkout[n].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) dev_err(&client->dev, "Cannot set rate : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ret = of_clk_add_hw_provider(client->dev.of_node, si53351_of_clk_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) dev_err(&client->dev, "unable to add clk provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static int si5351_i2c_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) of_clk_del_provider(client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static const struct i2c_device_id si5351_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) { "si5351a", SI5351_VARIANT_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) { "si5351a-msop", SI5351_VARIANT_A3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) { "si5351b", SI5351_VARIANT_B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) { "si5351c", SI5351_VARIANT_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static struct i2c_driver si5351_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .name = "si5351",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .of_match_table = of_match_ptr(si5351_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .probe = si5351_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .remove = si5351_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .id_table = si5351_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) module_i2c_driver(si5351_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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