^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 Topic Embedded Products
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Mike Looijmans <mike.looijmans@topic.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * The Si5341 has 10 outputs and 5 synthesizers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The Si5345 is similar to the Si5341, with the addition of fractional input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * dividers and automatic input selection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The Si5342 and Si5344 are smaller versions of the Si5345.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SI5341_NUM_INPUTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SI5340_MAX_NUM_OUTPUTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SI5341_MAX_NUM_OUTPUTS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SI5342_MAX_NUM_OUTPUTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SI5344_MAX_NUM_OUTPUTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SI5345_MAX_NUM_OUTPUTS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SI5340_NUM_SYNTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SI5341_NUM_SYNTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SI5342_NUM_SYNTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SI5344_NUM_SYNTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SI5345_NUM_SYNTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Range of the synthesizer fractional divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SI5341_SYNTH_N_MIN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SI5341_SYNTH_N_MAX 4095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* The chip can get its input clock from 3 input pins or an XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* There is one PLL running at 13500–14256 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SI5341_PLL_VCO_MIN 13500000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SI5341_PLL_VCO_MAX 14256000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* The 5 frequency synthesizers obtain their input from the PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk_si5341_synth {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk_si5341 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define to_clk_si5341_synth(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) container_of(_hw, struct clk_si5341_synth, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* The output stages can be connected to any synth (full mux) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk_si5341_output {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk_si5341 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define to_clk_si5341_output(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) container_of(_hw, struct clk_si5341_output, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_si5341 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk *input_clk[SI5341_NUM_INPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const char *input_clk_name[SI5341_NUM_INPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const u16 *reg_output_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const u16 *reg_rdiv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u64 freq_vco; /* 13500–14256 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 num_outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 num_synth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u16 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct clk_si5341_output_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 out_format_drv_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 out_cm_ampl_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bool synth_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) bool always_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SI5341_PAGE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SI5341_PN_BASE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SI5341_DEVICE_REV 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SI5341_STATUS 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SI5341_LOS 0x000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SI5341_STATUS_STICKY 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SI5341_LOS_STICKY 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SI5341_SOFT_RST 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SI5341_IN_SEL 0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SI5341_DEVICE_READY 0x00FE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SI5341_XAXB_CFG 0x090E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SI5341_IN_EN 0x0949
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SI5341_INX_TO_PFD_EN 0x094A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SI5341_STATUS_SYSINCAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SI5341_STATUS_LOSXAXB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SI5341_STATUS_LOSREF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SI5341_STATUS_LOL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Input selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SI5341_IN_SEL_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SI5341_IN_SEL_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SI5341_IN_SEL_REGCTRL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SI5341_INX_TO_PFD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* XTAL config bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SI5341_XAXB_CFG_PDNB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Input dividers (48-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SI5341_PX_UPD 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* PLL configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SI5341_PLL_M_NUM 0x0235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SI5341_PLL_M_DEN 0x023B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Output configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SI5341_OUT_CONFIG(output) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ((output)->data->reg_output_offset[(output)->index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SI5341_OUT_R_REG(output) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ((output)->data->reg_rdiv_offset[(output)->index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Synthesize N divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Synthesizer output enable, phase bypass, power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SI5341_SYNTH_N_PIBYP 0x0A04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SI5341_SYNTH_N_PDNB 0x0A05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SI5341_REGISTER_MAX 0xBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* SI5341_OUT_CONFIG bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SI5341_OUT_CFG_PDN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SI5341_OUT_CFG_OE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Static configuration (to be moved to firmware) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct si5341_reg_default {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u16 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const char * const si5341_input_clock_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "in0", "in1", "in2", "xtal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Output configuration registers 0..9 are not quite logically organized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Also for si5345 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const u16 si5341_reg_output_offset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0x010D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0x0112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0x0117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0x011C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0x0121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0x0126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x012B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0x0130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0x013A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* for si5340, si5342 and si5344 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const u16 si5340_reg_output_offset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0x0112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 0x0117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0x0126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x012B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* The location of the R divider registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const u16 si5341_reg_rdiv_offset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0x024A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0x024D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0x0250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x0253,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x0256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0x0259,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x025C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0x025F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x0262,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0x0268,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const u16 si5340_reg_rdiv_offset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 0x0250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0x0253,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 0x025C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x025F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Programming sequence from ClockBuilder, settings to initialize the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * using only the XTAL input, without pre-divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * This also contains settings that aren't mentioned anywhere in the datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * The "known" settings like synth and output configuration are done later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct si5341_reg_default si5341_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0x0018, 0xFF }, /* INT mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0x0021, 0x0F }, /* Select XTAL as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 0x0022, 0x00 }, /* Not in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 0x002B, 0x02 }, /* SPI config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0x002C, 0x20 }, /* LOS enable for XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 0x002D, 0x00 }, /* LOS timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 0x002E, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0x002F, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { 0x0030, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0x0031, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0x0032, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0x0033, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x0034, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x0035, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x0036, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x0037, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x0038, 0x00 }, /* LOS setting (thresholds) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0x0039, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x003A, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0x003B, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x003C, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 0x009E, 0x00 }, /* Not in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0x0102, 0x01 }, /* Enable outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 0x013F, 0x00 }, /* Not in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0x0140, 0x00 }, /* Not in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 0x0141, 0x40 }, /* OUT LOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 0x0203, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 0x0204, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 0x0205, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 0x0206, 0x00 }, /* PXAXB (2^x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 0x0209, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 0x020A, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 0x020B, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 0x020C, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 0x020D, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 0x020E, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 0x020F, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { 0x0210, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { 0x0211, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 0x0212, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 0x0213, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0x0214, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { 0x0215, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { 0x0216, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { 0x0217, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 0x0218, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { 0x0219, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 0x021A, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { 0x021B, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 0x021C, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { 0x021D, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 0x021E, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { 0x021F, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 0x0220, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 0x0221, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 0x0222, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { 0x0223, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { 0x0224, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { 0x0225, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { 0x0226, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { 0x0227, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { 0x0228, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { 0x0229, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { 0x022A, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { 0x022B, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { 0x022C, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { 0x022D, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { 0x022E, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { 0x026C, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { 0x026D, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { 0x026E, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { 0x026F, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { 0x0270, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { 0x0271, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { 0x0339, 0x1F }, /* N_FSTEP_MSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { 0x033C, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { 0x033D, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { 0x033E, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { 0x033F, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 0x0340, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 0x0341, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 0x0342, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 0x0343, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0x0344, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 0x0345, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 0x0346, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 0x0347, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 0x0348, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 0x0349, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 0x034A, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 0x034B, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 0x034C, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 0x034D, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 0x034E, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 0x034F, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 0x0350, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 0x0351, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 0x0352, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 0x0353, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 0x0354, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 0x0355, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 0x0356, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 0x0357, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 0x0359, 0x00 }, /* Nx_DELAY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 0x035A, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 0x035B, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 0x035C, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 0x035D, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 0x035E, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 0x035F, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { 0x0360, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 0x0361, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { 0x0362, 0x00 }, /* Nx_DELAY end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 0x0802, 0x00 }, /* Not in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 0x0803, 0x00 }, /* Not in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 0x0804, 0x00 }, /* Not in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { 0x0A02, 0x00 }, /* Not in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u64 *val1, u32 *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 r[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err = regmap_bulk_read(regmap, reg, r, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) (get_unaligned_le32(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *val2 = get_unaligned_le32(&r[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u64 n_num, u32 n_den)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 r[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Shift left as far as possible without overflowing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) n_num <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) n_den <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* 44 bits (6 bytes) numerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) put_unaligned_le32(n_num, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) r[4] = (n_num >> 32) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) r[5] = (n_num >> 40) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* 32 bits denominator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) put_unaligned_le32(n_den, &r[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Program the fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return regmap_bulk_write(regmap, reg, r, sizeof(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* VCO, we assume it runs at a constant frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct clk_si5341 *data = to_clk_si5341(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u64 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u64 m_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 m_den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Assume that PDIV is not being used, just read the PLL setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) &m_num, &m_den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!m_num || !m_den)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Though m_num is 64-bit, only the upper bits are actually used. While
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * calculating m_num and m_den, they are shifted as far as possible to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * the left. To avoid 96-bit division here, we just shift them back so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * we can do with just 64 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) res = m_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) while (res & 0xffff00000000ULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ++shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) res >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) res *= parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) do_div(res, (m_den >> shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* We cannot return the actual frequency in 32 bit, store it locally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) data->freq_vco = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Report kHz since the value is out of range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) do_div(res, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return (unsigned long)res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int si5341_clk_get_selected_input(struct clk_si5341 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static u8 si5341_clk_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct clk_si5341 *data = to_clk_si5341(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int res = si5341_clk_get_selected_input(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0; /* Apparently we cannot report errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Enable register-based input selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) val |= SI5341_IN_SEL_REGCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) err = regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (index < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Enable input buffer for selected input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) err = regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SI5341_IN_EN, 0x07, BIT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Enables the input to phase detector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 0x7 << SI5341_INX_TO_PFD_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) BIT(index + SI5341_INX_TO_PFD_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Power down XTAL oscillator and buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SI5341_XAXB_CFG_PDNB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Set the P divider to "1". There's no explanation in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * datasheet of these registers, but the clockbuilder software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * programs a "1" when the input is being used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Set update PDIV bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Disable all input buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Disable input to phase detector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Power up XTAL oscillator and buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct clk_si5341 *data = to_clk_si5341(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return si5341_clk_reparent(data, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct clk_ops si5341_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .set_parent = si5341_clk_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .get_parent = si5341_clk_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .recalc_rate = si5341_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* The synthesizer is on if all power and enable bits are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int si5341_synth_clk_is_on(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 index = synth->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) err = regmap_read(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!(val & BIT(index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!(val & BIT(index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* This bit must be 0 for the synthesizer to receive clock input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return !(val & BIT(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static void si5341_synth_clk_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u8 index = synth->index; /* In range 0..5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 mask = BIT(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Disable output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) regmap_update_bits(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) regmap_update_bits(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) SI5341_SYNTH_N_PDNB, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Disable clock input to synth (set to 1 to disable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) regmap_update_bits(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) SI5341_SYNTH_N_CLK_DIS, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int si5341_synth_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 index = synth->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u8 mask = BIT(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) err = regmap_update_bits(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) SI5341_SYNTH_N_PDNB, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Enable clock input to synth (set bit to 0 to enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) err = regmap_update_bits(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SI5341_SYNTH_N_CLK_DIS, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Enable output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return regmap_update_bits(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u64 f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u64 n_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 n_den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) err = si5341_decode_44_32(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Check for bogus/uninitialized settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!n_num || !n_den)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * n_num and n_den are shifted left as much as possible, so to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * overflow in 64-bit math, we shift n_den 4 bits to the right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) f = synth->data->freq_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) f *= n_den >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Now we need to to 64-bit division: f/n_num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* And compensate for the 4 bits we dropped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) f = div64_u64(f, (n_num >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u64 f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* The synthesizer accuracy is such that anything in range will work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) f = synth->data->freq_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) do_div(f, SI5341_SYNTH_N_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (rate < f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) f = synth->data->freq_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) do_div(f, SI5341_SYNTH_N_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (rate > f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int si5341_synth_program(struct clk_si5341_synth *synth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u64 n_num, u32 n_den, bool is_integer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 index = synth->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) err = si5341_encode_44_32(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) SI5341_SYNTH_N_NUM(index), n_num, n_den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) err = regmap_update_bits(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return regmap_write(synth->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) SI5341_SYNTH_N_UPD(index), 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u64 n_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u32 n_den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u32 g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) bool is_integer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) n_num = synth->data->freq_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* see if there's an integer solution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) r = do_div(n_num, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) is_integer = (r == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (is_integer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Integer divider equal to n_num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) n_den = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Calculate a fractional solution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) g = gcd(r, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) n_den = rate / g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) n_num *= n_den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) n_num += r / g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_dbg(&synth->data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) synth->index, n_num, n_den,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) is_integer ? "int" : "frac");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return si5341_synth_program(synth, n_num, n_den, is_integer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const struct clk_ops si5341_synth_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .is_prepared = si5341_synth_clk_is_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .prepare = si5341_synth_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .unprepare = si5341_synth_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .recalc_rate = si5341_synth_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .round_rate = si5341_synth_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .set_rate = si5341_synth_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static int si5341_output_clk_is_on(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct clk_si5341_output *output = to_clk_si5341_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) err = regmap_read(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) SI5341_OUT_CONFIG(output), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return (val & 0x03) == SI5341_OUT_CFG_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Disables and then powers down the output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static void si5341_output_clk_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct clk_si5341_output *output = to_clk_si5341_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) regmap_update_bits(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) SI5341_OUT_CONFIG(output),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) SI5341_OUT_CFG_OE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) regmap_update_bits(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) SI5341_OUT_CONFIG(output),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* Powers up and then enables the output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int si5341_output_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct clk_si5341_output *output = to_clk_si5341_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) err = regmap_update_bits(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) SI5341_OUT_CONFIG(output),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) SI5341_OUT_CFG_PDN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return regmap_update_bits(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) SI5341_OUT_CONFIG(output),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct clk_si5341_output *output = to_clk_si5341_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u32 r_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u8 r[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) err = regmap_bulk_read(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SI5341_OUT_R_REG(output), r, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Calculate value as 24-bit integer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) r_divider = r[2] << 16 | r[1] << 8 | r[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!r_divider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Divider is 2*(Rx_REG+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) r_divider += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) r_divider <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) err = regmap_read(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) SI5341_OUT_CONFIG(output), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (val & SI5341_OUT_CFG_RDIV_FORCE2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) r_divider = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return parent_rate / r_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) r = *parent_rate >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* If rate is an even divisor, no changes to parent required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (r && !(r % rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return (long)rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (rate > 200000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* minimum r-divider is 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) r = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Take a parent frequency near 400 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) r = (400000000u / rate) & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) *parent_rate = r * rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* We cannot change our parent's rate, report what we can do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) r /= rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) rate = *parent_rate / (r << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct clk_si5341_output *output = to_clk_si5341_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u32 r_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u8 r[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Frequency divider is (r_div + 1) * 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) r_div = (parent_rate / rate) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (r_div <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) r_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) else if (r_div >= BIT(24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) r_div = BIT(24) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) --r_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) err = regmap_update_bits(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) SI5341_OUT_CONFIG(output),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) SI5341_OUT_CFG_RDIV_FORCE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Always write Rx_REG, because a zero value disables the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) r[0] = r_div ? (r_div & 0xff) : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) r[1] = (r_div >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) r[2] = (r_div >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) err = regmap_bulk_write(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) SI5341_OUT_R_REG(output), r, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return regmap_update_bits(output->data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) SI5341_OUT_MUX_SEL(output), 0x07, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct clk_si5341_output *output = to_clk_si5341_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (index >= output->data->num_synth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return si5341_output_reparent(output, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static u8 si5341_output_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct clk_si5341_output *output = to_clk_si5341_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return val & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const struct clk_ops si5341_output_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .is_prepared = si5341_output_clk_is_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .prepare = si5341_output_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .unprepare = si5341_output_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .recalc_rate = si5341_output_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .round_rate = si5341_output_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .set_rate = si5341_output_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .set_parent = si5341_output_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .get_parent = si5341_output_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * The chip can be bought in a pre-programmed version, or one can program the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * NVM in the chip to boot up in a preset mode. This routine tries to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * if that's the case, or if we need to reset and program everything from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * scratch. Returns negative error, or true/false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int si5341_is_programmed_already(struct clk_si5341 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u8 r[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* Read the PLL divider value, it must have a non-zero value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) r, ARRAY_SIZE(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return !!get_unaligned_le32(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct clk_si5341 *data = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) unsigned int idx = clkspec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) unsigned int group = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) switch (group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (idx >= data->num_outputs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_err(&data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "invalid output index %u\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return &data->clk[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (idx >= data->num_synth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_err(&data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) "invalid synthesizer index %u\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return &data->synth[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (idx > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dev_err(&data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) "invalid PLL index %u\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return &data->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static int si5341_probe_chip_id(struct clk_si5341 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u8 reg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u16 model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ARRAY_SIZE(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) model = get_unaligned_le16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) model, reg[2], reg[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) switch (model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case 0x5340:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) data->num_synth = SI5340_NUM_SYNTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) data->reg_output_offset = si5340_reg_output_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) data->reg_rdiv_offset = si5340_reg_rdiv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) case 0x5341:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) data->num_synth = SI5341_NUM_SYNTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) data->reg_output_offset = si5341_reg_output_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) data->reg_rdiv_offset = si5341_reg_rdiv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) case 0x5342:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) data->num_synth = SI5342_NUM_SYNTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) data->reg_output_offset = si5340_reg_output_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) data->reg_rdiv_offset = si5340_reg_rdiv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) case 0x5344:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) data->num_synth = SI5344_NUM_SYNTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) data->reg_output_offset = si5340_reg_output_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) data->reg_rdiv_offset = si5340_reg_rdiv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case 0x5345:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) data->num_synth = SI5345_NUM_SYNTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) data->reg_output_offset = si5341_reg_output_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) data->reg_rdiv_offset = si5341_reg_rdiv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) data->chip_id = model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* Read active settings into the regmap cache for later reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int si5341_read_settings(struct clk_si5341 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u8 r[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) err = regmap_bulk_read(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) err = regmap_bulk_read(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) SI5341_SYNTH_N_CLK_DIS, r, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) for (i = 0; i < data->num_synth; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) err = regmap_bulk_read(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) SI5341_SYNTH_N_NUM(i), r, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) for (i = 0; i < data->num_outputs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) err = regmap_bulk_read(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) data->reg_output_offset[i], r, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) err = regmap_bulk_read(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) data->reg_rdiv_offset[i], r, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int si5341_write_multiple(struct clk_si5341 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) const struct si5341_reg_default *values, unsigned int num_values)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) for (i = 0; i < num_values; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) res = regmap_write(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) values[i].address, values[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_err(&data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "Failed to write %#x:%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) values[i].address, values[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static const struct si5341_reg_default si5341_preamble[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) { 0x0B25, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) { 0x0502, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) { 0x0505, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) { 0x0957, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) { 0x0B4E, 0x1A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static const struct si5341_reg_default si5345_preamble[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) { 0x0B25, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) { 0x0540, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static int si5341_send_preamble(struct clk_si5341 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* For revision 2 and up, the values are slightly different */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* Write "preamble" as specified by datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* The si5342..si5345 require a different preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (data->chip_id > 0x5341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) res = si5341_write_multiple(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) si5345_preamble, ARRAY_SIZE(si5345_preamble));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) res = si5341_write_multiple(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) si5341_preamble, ARRAY_SIZE(si5341_preamble));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* Datasheet specifies a 300ms wait after sending the preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) msleep(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* Perform a soft reset and write post-amble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static int si5341_finalize_defaults(struct clk_si5341 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* The si5342..si5345 have an additional post-amble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (data->chip_id > 0x5341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) res = regmap_write(data->regmap, 0x540, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Datasheet does not explain these nameless registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) res = regmap_write(data->regmap, 0x0B25, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static const struct regmap_range si5341_regmap_volatile_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) regmap_reg_range(0x000C, 0x0012), /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* Update bits for P divider and synth config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static const struct regmap_access_table si5341_regmap_volatile = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .yes_ranges = si5341_regmap_volatile_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static const struct regmap_range_cfg si5341_regmap_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .range_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .range_max = SI5341_REGISTER_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .selector_reg = SI5341_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .selector_mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .selector_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .window_start = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .window_len = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static int si5341_wait_device_ready(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Datasheet warns: Any attempt to read or write any register other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * NVM programming and may corrupt the register contents, as they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * read from NVM. Note that this includes accesses to the PAGE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * Also: DEVICE_READY is available on every register page, so no page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * change is needed to read it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * Do this outside regmap to avoid automatic PAGE register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * May take up to 300ms to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) for (count = 0; count < 15; ++count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) s32 result = i2c_smbus_read_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) SI5341_DEVICE_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (result == 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static const struct regmap_config si5341_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .ranges = si5341_regmap_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .max_register = SI5341_REGISTER_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .volatile_table = &si5341_regmap_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static int si5341_dt_parse_dt(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct clk_si5341_output_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct device_node *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u32 num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) memset(config, 0, sizeof(struct clk_si5341_output_config) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) SI5341_MAX_NUM_OUTPUTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (of_property_read_u32(child, "reg", &num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_err(&client->dev, "missing reg property of %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) child->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (num >= SI5341_MAX_NUM_OUTPUTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) dev_err(&client->dev, "invalid clkout %d\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!of_property_read_u32(child, "silabs,format", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* Set cm and ampl conservatively to 3v3 settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) case 1: /* normal differential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) config[num].out_cm_ampl_bits = 0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case 2: /* low-power differential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) config[num].out_cm_ampl_bits = 0x13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) case 4: /* LVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) config[num].out_cm_ampl_bits = 0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* Set SI recommended impedance for LVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) config[num].out_format_drv_bits |= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) "invalid silabs,format %u for %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) val, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) config[num].out_format_drv_bits &= ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) config[num].out_format_drv_bits |= val & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* Always enable the SYNC feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) config[num].out_format_drv_bits |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (val > 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) "invalid silabs,common-mode %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) config[num].out_cm_ampl_bits &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) config[num].out_cm_ampl_bits |= val & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (val > 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) "invalid silabs,amplitude %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) config[num].out_cm_ampl_bits &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (of_property_read_bool(child, "silabs,disable-high"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) config[num].out_format_drv_bits |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) config[num].synth_master =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) of_property_read_bool(child, "silabs,synth-master");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) config[num].always_on =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) of_property_read_bool(child, "always-on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * If not pre-configured, calculate and set the PLL configuration manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * For low-jitter performance, the PLL should be set such that the synthesizers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * only need integer division.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * Without any user guidance, we'll set the PLL to 14GHz, which still allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * the chip to generate any frequency on its outputs, but jitter performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * may be sub-optimal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static int si5341_initialize_pll(struct clk_si5341 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) struct device_node *np = data->i2c_client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) u32 m_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) u32 m_den = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_err(&data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) "PLL configuration requires silabs,pll-m-num\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dev_err(&data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) "PLL configuration requires silabs,pll-m-den\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (!m_num || !m_den) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dev_err(&data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) "PLL configuration invalid, assume 14GHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) sel = si5341_clk_get_selected_input(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (sel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) m_den = clk_get_rate(data->input_clk[sel]) / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) m_num = 1400000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return si5341_encode_44_32(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) SI5341_PLL_M_NUM, m_num, m_den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static int si5341_clk_select_active_input(struct clk_si5341 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) res = si5341_clk_get_selected_input(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* If the current register setting is invalid, pick the first input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (!data->input_clk[res]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dev_dbg(&data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) "Input %d not connected, rerouting\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) res = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (data->input_clk[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) res = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dev_err(&data->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) "No clock input available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* Make sure the selected clock is also enabled and routed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) err = si5341_clk_reparent(data, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) err = clk_prepare_enable(data->input_clk[res]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static int si5341_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct clk_si5341 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct clk *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) const char *root_clock_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) const char *synth_clock_names[SI5341_NUM_SYNTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) bool initialization_required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) data->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* Must be done before otherwise touching hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) err = si5341_wait_device_ready(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (IS_ERR(input)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (PTR_ERR(input) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) data->input_clk_name[i] = si5341_input_clock_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) data->input_clk[i] = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) data->input_clk_name[i] = __clk_get_name(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) err = si5341_dt_parse_dt(client, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (of_property_read_string(client->dev.of_node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) &init.name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) init.name = client->dev.of_node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) root_clock_name = init.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (IS_ERR(data->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) err = si5341_probe_chip_id(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) initialization_required = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) err = si5341_is_programmed_already(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) initialization_required = !err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (initialization_required) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* Populate the regmap cache in preparation for "cache only" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) err = si5341_read_settings(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) err = si5341_send_preamble(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * We intend to send all 'final' register values in a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * transaction. So cache all register writes until we're done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) * configuring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) regcache_cache_only(data->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* Write the configuration pairs from the firmware blob */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) err = si5341_write_multiple(data, si5341_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ARRAY_SIZE(si5341_reg_defaults));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* Input must be up and running at this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) err = si5341_clk_select_active_input(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (initialization_required) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /* PLL configuration is required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) err = si5341_initialize_pll(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* Register the PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) init.parent_names = data->input_clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) init.num_parents = SI5341_NUM_INPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) init.ops = &si5341_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) data->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) err = devm_clk_hw_register(&client->dev, &data->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dev_err(&client->dev, "clock registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) init.parent_names = &root_clock_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) init.ops = &si5341_synth_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) for (i = 0; i < data->num_synth; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) "%s.N%u", client->dev.of_node->name, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) init.name = synth_clock_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) data->synth[i].index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) data->synth[i].data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) data->synth[i].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) "synth N%u registration failed\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) init.num_parents = data->num_synth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) init.parent_names = synth_clock_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) init.ops = &si5341_output_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) for (i = 0; i < data->num_outputs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) init.name = kasprintf(GFP_KERNEL, "%s.%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) client->dev.of_node->name, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) data->clk[i].index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) data->clk[i].data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) data->clk[i].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (config[i].out_format_drv_bits & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) regmap_write(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SI5341_OUT_FORMAT(&data->clk[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) config[i].out_format_drv_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) regmap_write(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) SI5341_OUT_CM(&data->clk[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) config[i].out_cm_ampl_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) "output %u registration failed\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (config[i].always_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) clk_prepare(data->clk[i].hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dev_err(&client->dev, "unable to add clk provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (initialization_required) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /* Synchronize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) regcache_cache_only(data->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) err = regcache_sync(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) err = si5341_finalize_defaults(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /* wait for device to report input clock present and PLL lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) 10000, 250000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* clear sticky alarm bits from initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) dev_err(&client->dev, "unable to clear sticky status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* Free the names, clk framework makes copies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) for (i = 0; i < data->num_synth; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) devm_kfree(&client->dev, (void *)synth_clock_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static const struct i2c_device_id si5341_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) { "si5340", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) { "si5341", 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) { "si5342", 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) { "si5344", 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) { "si5345", 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) MODULE_DEVICE_TABLE(i2c, si5341_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) static const struct of_device_id clk_si5341_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) { .compatible = "silabs,si5340" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) { .compatible = "silabs,si5341" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) { .compatible = "silabs,si5342" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) { .compatible = "silabs,si5344" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) { .compatible = "silabs,si5345" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static struct i2c_driver si5341_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .name = "si5341",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .of_match_table = clk_si5341_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .probe = si5341_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .id_table = si5341_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) module_i2c_driver(si5341_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) MODULE_DESCRIPTION("Si5341 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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