^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Silicon Labs Si514 Programmable Oscillator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Topic Embedded Products
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Mike Looijmans <mike.looijmans@topic.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* I2C registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SI514_REG_LP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SI514_REG_M_FRAC1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SI514_REG_M_FRAC2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SI514_REG_M_FRAC3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SI514_REG_M_INT_FRAC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SI514_REG_M_INT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SI514_REG_HS_DIV 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SI514_REG_LS_HS_DIV 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SI514_REG_OE_STATE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SI514_REG_RESET 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SI514_REG_CONTROL 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SI514_RESET_RST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SI514_CONTROL_FCAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SI514_CONTROL_OE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SI514_MIN_FREQ 100000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SI514_MAX_FREQ 250000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FXO 31980000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FVCO_MIN 2080000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FVCO_MAX 2500000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HS_DIV_MAX 1022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk_si514 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define to_clk_si514(_hw) container_of(_hw, struct clk_si514, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Multiplier/divider settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk_si514_muldiv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 m_frac; /* 29-bit Fractional part of multiplier M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 m_int; /* Integer part of multiplier M, 65..78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 ls_div_bits; /* 2nd divider, as 2^x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 hs_div; /* 1st divider, must be even and 10<=x<=1022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Enables or disables the output driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int si514_enable_output(struct clk_si514 *data, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return regmap_update_bits(data->regmap, SI514_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SI514_CONTROL_OE, enable ? SI514_CONTROL_OE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int si514_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk_si514 *data = to_clk_si514(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return si514_enable_output(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void si514_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk_si514 *data = to_clk_si514(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) si514_enable_output(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int si514_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct clk_si514 *data = to_clk_si514(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) err = regmap_read(data->regmap, SI514_REG_CONTROL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return !!(val & SI514_CONTROL_OE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Retrieve clock multiplier and dividers from hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int si514_get_muldiv(struct clk_si514 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct clk_si514_muldiv *settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 reg[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) err = regmap_bulk_read(data->regmap, SI514_REG_M_FRAC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg, ARRAY_SIZE(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) settings->m_frac = reg[0] | reg[1] << 8 | reg[2] << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (reg[3] & 0x1F) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) settings->m_int = (reg[4] & 0x3f) << 3 | reg[3] >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) settings->ls_div_bits = (reg[6] >> 4) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) settings->hs_div = (reg[6] & 0x03) << 8 | reg[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int si514_set_muldiv(struct clk_si514 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk_si514_muldiv *settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 reg[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Calculate LP1/LP2 according to table 13 in the datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* 65.259980246 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (settings->m_int < 65 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (settings->m_int == 65 && settings->m_frac <= 139575831))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) lp = 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* 67.859763463 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else if (settings->m_int < 67 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) (settings->m_int == 67 && settings->m_frac <= 461581994))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) lp = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* 72.937624981 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else if (settings->m_int < 72 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (settings->m_int == 72 && settings->m_frac <= 503383578))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) lp = 0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 75.843265046 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) else if (settings->m_int < 75 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (settings->m_int == 75 && settings->m_frac <= 452724474))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) lp = 0x34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) lp = 0x44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = regmap_write(data->regmap, SI514_REG_LP, lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg[0] = settings->m_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reg[1] = settings->m_frac >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg[2] = settings->m_frac >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg[3] = settings->m_frac >> 24 | settings->m_int << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg[4] = settings->m_int >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg[5] = settings->hs_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg[6] = (settings->hs_div >> 8) | (settings->ls_div_bits << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) err = regmap_bulk_write(data->regmap, SI514_REG_HS_DIV, reg + 5, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Writing to SI514_REG_M_INT_FRAC triggers the clock change, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * must be written last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return regmap_bulk_write(data->regmap, SI514_REG_M_FRAC1, reg, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Calculate divider settings for a given frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int si514_calc_muldiv(struct clk_si514_muldiv *settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u64 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 ls_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if ((frequency < SI514_MIN_FREQ) || (frequency > SI514_MAX_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Determine the minimum value of LS_DIV and resulting target freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ls_freq = frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (frequency >= (FVCO_MIN / HS_DIV_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) settings->ls_div_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) res = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tmp = 2 * HS_DIV_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) while (tmp <= (HS_DIV_MAX * 32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if ((frequency * tmp) >= FVCO_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ++res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tmp <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) settings->ls_div_bits = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ls_freq = frequency << res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Determine minimum HS_DIV, round up to even number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) settings->hs_div = DIV_ROUND_UP(FVCO_MIN >> 1, ls_freq) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* M = LS_DIV x HS_DIV x frequency / F_XO (in fixed-point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) m = ((u64)(ls_freq * settings->hs_div) << 29) + (FXO / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) do_div(m, FXO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) settings->m_frac = (u32)m & (BIT(29) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) settings->m_int = (u32)(m >> 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Calculate resulting frequency given the register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static unsigned long si514_calc_rate(struct clk_si514_muldiv *settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u64 m = settings->m_frac | ((u64)settings->m_int << 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 d = settings->hs_div * BIT(settings->ls_div_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ((u32)(((m * FXO) + (FXO / 2)) >> 29)) / d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static unsigned long si514_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct clk_si514 *data = to_clk_si514(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct clk_si514_muldiv settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) err = si514_get_muldiv(data, &settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(&data->i2c_client->dev, "unable to retrieve settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return si514_calc_rate(&settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static long si514_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct clk_si514_muldiv settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err = si514_calc_muldiv(&settings, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return si514_calc_rate(&settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Update output frequency for big frequency changes (> 1000 ppm).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * The chip supports <1000ppm changes "on the fly", we haven't implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * that here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int si514_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct clk_si514 *data = to_clk_si514(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct clk_si514_muldiv settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned int old_oe_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err = si514_calc_muldiv(&settings, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) err = regmap_read(data->regmap, SI514_REG_CONTROL, &old_oe_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) si514_enable_output(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) err = si514_set_muldiv(data, &settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return err; /* Undefined state now, best to leave disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Trigger calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) err = regmap_write(data->regmap, SI514_REG_CONTROL, SI514_CONTROL_FCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Applying a new frequency can take up to 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) usleep_range(10000, 12000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (old_oe_state & SI514_CONTROL_OE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) si514_enable_output(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct clk_ops si514_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .prepare = si514_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .unprepare = si514_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .is_prepared = si514_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .recalc_rate = si514_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .round_rate = si514_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .set_rate = si514_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static bool si514_regmap_is_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case SI514_REG_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case SI514_REG_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static bool si514_regmap_is_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case SI514_REG_LP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case SI514_REG_M_FRAC1 ... SI514_REG_LS_HS_DIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case SI514_REG_OE_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case SI514_REG_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case SI514_REG_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct regmap_config si514_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .max_register = SI514_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .writeable_reg = si514_regmap_is_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .volatile_reg = si514_regmap_is_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int si514_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct clk_si514 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) init.ops = &si514_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) data->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) data->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (of_property_read_string(client->dev.of_node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &init.name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) init.name = client->dev.of_node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) data->regmap = devm_regmap_init_i2c(client, &si514_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(&client->dev, "failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) err = devm_clk_hw_register(&client->dev, &data->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(&client->dev, "clock registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err = of_clk_add_hw_provider(client->dev.of_node, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) &data->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_err(&client->dev, "unable to add clk provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int si514_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) of_clk_del_provider(client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct i2c_device_id si514_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { "si514", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MODULE_DEVICE_TABLE(i2c, si514_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct of_device_id clk_si514_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { .compatible = "silabs,si514" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_DEVICE_TABLE(of, clk_si514_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct i2c_driver si514_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .name = "si514",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .of_match_table = clk_si514_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .probe = si514_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .remove = si514_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .id_table = si514_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) module_i2c_driver(si514_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_DESCRIPTION("Si514 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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