^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * System Control and Power Interface (SCPI) Protocol based clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/scpi_protocol.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct scpi_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct scpi_dvfs_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct scpi_ops *scpi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct platform_device *cpufreq_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct scpi_clk *clk = to_scpi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return clk->scpi_ops->clk_get_val(clk->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * We can't figure out what rate it will be, so just return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * rate back to the caller. scpi_clk_recalc_rate() will be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * after the rate is set and we'll know what rate the clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * running at then.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct scpi_clk *clk = to_scpi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return clk->scpi_ops->clk_set_val(clk->id, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct clk_ops scpi_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .recalc_rate = scpi_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .round_rate = scpi_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .set_rate = scpi_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* find closest match to given frequency in OPP table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static long __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long fmin = 0, fmax = ~0, ftmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const struct scpi_opp *opp = clk->info->opps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) for (idx = 0; idx < clk->info->count; idx++, opp++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ftmp = opp->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (ftmp >= rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (ftmp <= fmax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) fmax = ftmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) } else if (ftmp >= fmin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) fmin = ftmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return fmax != ~0 ? fmax : fmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct scpi_clk *clk = to_scpi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const struct scpi_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) opp = clk->info->opps + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return opp->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct scpi_clk *clk = to_scpi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return __scpi_dvfs_round_rate(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int idx, max_opp = clk->info->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct scpi_opp *opp = clk->info->opps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) for (idx = 0; idx < max_opp; idx++, opp++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (opp->freq == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int scpi_dvfs_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct scpi_clk *clk = to_scpi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int ret = __scpi_find_dvfs_index(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct clk_ops scpi_dvfs_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .recalc_rate = scpi_dvfs_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .round_rate = scpi_dvfs_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .set_rate = scpi_dvfs_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct of_device_id scpi_clk_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .compatible = "arm,scpi-dvfs-clocks", .data = &scpi_dvfs_ops, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .compatible = "arm,scpi-variable-clocks", .data = &scpi_clk_ops, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) scpi_clk_ops_init(struct device *dev, const struct of_device_id *match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct scpi_clk *sclk, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long min = 0, max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) init.ops = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sclk->scpi_ops = get_scpi_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (init.ops == &scpi_dvfs_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (IS_ERR(sclk->info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return PTR_ERR(sclk->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } else if (init.ops == &scpi_clk_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = devm_clk_hw_register(dev, &sclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!ret && max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk_hw_set_rate_range(&sclk->hw, min, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct scpi_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct scpi_clk **clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) scpi_of_clk_src_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct scpi_clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct scpi_clk_data *clk_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int idx = clkspec->args[0], count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) for (count = 0; count < clk_data->clk_num; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) sclk = clk_data->clk[count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (idx == sclk->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return &sclk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int scpi_clk_add(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const struct of_device_id *match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int idx, count, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct scpi_clk_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) count = of_property_count_strings(np, "clock-output-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (count < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(dev, "%pOFn: invalid clock output count\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk_data->clk_num = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!clk_data->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) for (idx = 0; idx < count; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct scpi_clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!sclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (of_property_read_string_index(np, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) idx, &name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(dev, "invalid clock name @ %pOFn\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (of_property_read_u32_index(np, "clock-indices",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) idx, &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(dev, "invalid clock index @ %pOFn\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) sclk->id = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err = scpi_clk_ops_init(dev, match, sclk, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dev, "failed to register clock '%s'\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_dbg(dev, "Registered clock '%s'\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clk_data->clk[idx] = sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return of_clk_add_hw_provider(np, scpi_of_clk_src_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int scpi_clocks_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct device_node *child, *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (cpufreq_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) platform_device_unregister(cpufreq_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cpufreq_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for_each_available_child_of_node(np, child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) of_clk_del_provider(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int scpi_clocks_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct device_node *child, *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!get_scpi_ops())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) match = of_match_node(scpi_clk_match, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = scpi_clk_add(dev, child, match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) scpi_clocks_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (match->data != &scpi_dvfs_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Add the virtual cpufreq device if it's DVFS clock provider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (IS_ERR(cpufreq_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pr_warn("unable to register cpufreq device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct of_device_id scpi_clocks_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { .compatible = "arm,scpi-clocks", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_DEVICE_TABLE(of, scpi_clocks_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct platform_driver scpi_clocks_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "scpi_clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .of_match_table = scpi_clocks_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .probe = scpi_clocks_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .remove = scpi_clocks_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) module_platform_driver(scpi_clocks_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MODULE_DESCRIPTION("ARM SCPI clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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