^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * System Control and Power Interface (SCMI) Protocol based clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018-2020 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/scmi_protocol.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const struct scmi_clk_proto_ops *clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct scmi_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) const struct scmi_clock_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) const struct scmi_protocol_handle *ph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define to_scmi_clk(clk) container_of(clk, struct scmi_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static unsigned long scmi_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct scmi_clk *clk = to_scmi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ret = clk_ops->rate_get(clk->ph, clk->id, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static long scmi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u64 fmin, fmax, ftmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct scmi_clk *clk = to_scmi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * We can't figure out what rate it will be, so just return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * rate back to the caller. scmi_clk_recalc_rate() will be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * after the rate is set and we'll know what rate the clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * running at then.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (clk->info->rate_discrete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) fmin = clk->info->range.min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) fmax = clk->info->range.max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (rate <= fmin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return fmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) else if (rate >= fmax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return fmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ftmp = rate - fmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ftmp += clk->info->range.step_size - 1; /* to round up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) do_div(ftmp, clk->info->range.step_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return ftmp * clk->info->range.step_size + fmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int scmi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct scmi_clk *clk = to_scmi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return clk_ops->rate_set(clk->ph, clk->id, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int scmi_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct scmi_clk *clk = to_scmi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return clk_ops->enable(clk->ph, clk->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void scmi_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct scmi_clk *clk = to_scmi_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk_ops->disable(clk->ph, clk->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct clk_ops scmi_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .recalc_rate = scmi_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .round_rate = scmi_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .set_rate = scmi_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * We can't provide enable/disable callback as we can't perform the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * in atomic context. Since the clock framework provides standard API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * clk_prepare_enable that helps cases using clk_enable in non-atomic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * context, it should be fine providing prepare/unprepare.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .prepare = scmi_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .unprepare = scmi_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long min_rate, max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .num_parents = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .ops = &scmi_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = sclk->info->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) sclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = devm_clk_hw_register(dev, &sclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (sclk->info->rate_discrete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int num_rates = sclk->info->list.num_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (num_rates <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) min_rate = sclk->info->list.rates[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) max_rate = sclk->info->list.rates[num_rates - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) min_rate = sclk->info->range.min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) max_rate = sclk->info->range.max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int scmi_clocks_probe(struct scmi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int idx, count, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct device *dev = &sdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const struct scmi_handle *handle = sdev->handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct scmi_protocol_handle *ph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk_ops = handle->devm_get_protocol(sdev, SCMI_PROTOCOL_CLOCK, &ph);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (IS_ERR(clk_ops))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return PTR_ERR(clk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) count = clk_ops->count_get(ph);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (count < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_err(dev, "%pOFn: invalid clock output count\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clk_data->num = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) hws = clk_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (idx = 0; idx < count; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct scmi_clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!sclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sclk->info = clk_ops->info_get(ph, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!sclk->info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_dbg(dev, "invalid clock info for idx %d\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) sclk->id = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sclk->ph = ph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) err = scmi_clk_ops_init(dev, sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_err(dev, "failed to register clock %d\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) devm_kfree(dev, sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) hws[idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_dbg(dev, "Registered clock:%s\n", sclk->info->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) hws[idx] = &sclk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct scmi_device_id scmi_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { SCMI_PROTOCOL_CLOCK, "clocks" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MODULE_DEVICE_TABLE(scmi, scmi_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct scmi_driver scmi_clocks_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "scmi-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .probe = scmi_clocks_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .id_table = scmi_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) module_scmi_driver(scmi_clocks_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MODULE_DESCRIPTION("ARM SCMI clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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