^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * clock driver for Freescale QorIQ SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/fsl/guts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_DIV1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_DIV2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_DIV3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_DIV4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLATFORM_PLL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CGA_PLL1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CGA_PLL2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CGA_PLL3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CGB_PLL1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CGB_PLL2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX_PLL_DIV 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clockgen_pll_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clockgen_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clockgen_pll_div div[MAX_PLL_DIV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLKSEL_VALID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clockgen_sourceinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 flags; /* CLKSEL_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int pll; /* CGx_PLLn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int div; /* PLL_DIVn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NUM_MUX_PARENTS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clockgen_muxinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define NUM_HWACCEL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NUM_CMUX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clockgen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * cmux freq must be >= platform pll.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * If not set, cmux freq must be >= platform pll/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CG_CMUX_GE_PLAT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CG_VER3 4 /* version 3 cg: reg layout different */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CG_LITTLE_ENDIAN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clockgen_chipinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const char *compat, *guts_compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const struct clockgen_muxinfo *cmux_groups[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void (*init_periph)(struct clockgen *cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 pll_mask; /* 1 << n bit set if PLL n is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 flags; /* CG_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct clockgen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clockgen_chipinfo info; /* mutable copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk *sysclk, *coreclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct clockgen_pll pll[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk *cmux[NUM_CMUX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk *hwaccel[NUM_HWACCEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *fman[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct ccsr_guts __iomem *guts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct clockgen clockgen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static bool add_cpufreq_dev __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (cg->info.flags & CG_LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) iowrite32(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) iowrite32be(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (cg->info.flags & CG_LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = ioread32be(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct clockgen_muxinfo p2041_cmux_grp1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct clockgen_muxinfo p2041_cmux_grp2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct clockgen_muxinfo p5020_cmux_grp1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct clockgen_muxinfo p5020_cmux_grp2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct clockgen_muxinfo p5040_cmux_grp1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct clockgen_muxinfo p5040_cmux_grp2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct clockgen_muxinfo p4080_cmux_grp1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct clockgen_muxinfo p4080_cmux_grp2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct clockgen_muxinfo t1023_cmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct clockgen_muxinfo t1040_cmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct clockgen_muxinfo clockgen2_cmux_cga = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct clockgen_muxinfo ls1021a_cmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct clockgen_muxinfo ls1028a_hwa1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct clockgen_muxinfo ls1028a_hwa2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct clockgen_muxinfo ls1028a_hwa3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct clockgen_muxinfo ls1028a_hwa4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct clockgen_muxinfo ls1043a_hwa1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct clockgen_muxinfo ls1043a_hwa2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct clockgen_muxinfo ls1046a_hwa1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct clockgen_muxinfo ls1046a_hwa2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct clockgen_muxinfo ls1088a_hwa1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct clockgen_muxinfo ls1088a_hwa2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct clockgen_muxinfo ls1012a_cmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct clockgen_muxinfo t1023_hwa1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const struct clockgen_muxinfo t1023_hwa2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct clockgen_muxinfo t2080_hwa1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const struct clockgen_muxinfo t2080_hwa2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct clockgen_muxinfo t4240_hwa1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct clockgen_muxinfo t4240_hwa4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct clockgen_muxinfo t4240_hwa5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define RCWSR7_FM1_CLK_SEL 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define RCWSR7_FM2_CLK_SEL 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define RCWSR7_HWA_ASYNC_DIV 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void __init p2041_init_periph(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) reg = ioread32be(&cg->guts->rcwsr[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (reg & RCWSR7_FM1_CLK_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void __init p4080_init_periph(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) reg = ioread32be(&cg->guts->rcwsr[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (reg & RCWSR7_FM1_CLK_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (reg & RCWSR7_FM2_CLK_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void __init p5020_init_periph(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int div = PLL_DIV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) reg = ioread32be(&cg->guts->rcwsr[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (reg & RCWSR7_HWA_ASYNC_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) div = PLL_DIV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (reg & RCWSR7_FM1_CLK_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static void __init p5040_init_periph(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int div = PLL_DIV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) reg = ioread32be(&cg->guts->rcwsr[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (reg & RCWSR7_HWA_ASYNC_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) div = PLL_DIV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (reg & RCWSR7_FM1_CLK_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (reg & RCWSR7_FM2_CLK_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void __init t1023_init_periph(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cg->fman[0] = cg->hwaccel[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static void __init t1040_init_periph(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void __init t2080_init_periph(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) cg->fman[0] = cg->hwaccel[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void __init t4240_init_periph(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cg->fman[0] = cg->hwaccel[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cg->fman[1] = cg->hwaccel[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct clockgen_chipinfo chipinfo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .compat = "fsl,b4420-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .guts_compat = "fsl,b4860-device-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .init_periph = t2080_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .hwaccel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) &t2080_hwa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 0, 1, 1, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .pll_mask = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .flags = CG_PLL_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .compat = "fsl,b4860-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .guts_compat = "fsl,b4860-device-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .init_periph = t2080_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .hwaccel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) &t2080_hwa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 0, 1, 1, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .pll_mask = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .flags = CG_PLL_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .compat = "fsl,ls1021a-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) &ls1021a_cmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .pll_mask = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .compat = "fsl,ls1028a-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) &clockgen2_cmux_cga12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .hwaccel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) &ls1028a_hwa1, &ls1028a_hwa2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) &ls1028a_hwa3, &ls1028a_hwa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 0, 0, 0, 0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .pll_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .flags = CG_VER3 | CG_LITTLE_ENDIAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .compat = "fsl,ls1043a-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .init_periph = t2080_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) &t1040_cmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .hwaccel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) &ls1043a_hwa1, &ls1043a_hwa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .pll_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .flags = CG_PLL_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .compat = "fsl,ls1046a-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .init_periph = t2080_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) &t1040_cmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .hwaccel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) &ls1046a_hwa1, &ls1046a_hwa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .pll_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .flags = CG_PLL_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .compat = "fsl,ls1088a-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &clockgen2_cmux_cga12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .hwaccel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) &ls1088a_hwa1, &ls1088a_hwa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 0, 0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .pll_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .flags = CG_VER3 | CG_LITTLE_ENDIAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .compat = "fsl,ls1012a-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) &ls1012a_cmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .pll_mask = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .compat = "fsl,ls2080a-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 0, 0, 1, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .pll_mask = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .flags = CG_VER3 | CG_LITTLE_ENDIAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .compat = "fsl,lx2160a-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 0, 0, 0, 0, 1, 1, 1, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .pll_mask = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .flags = CG_VER3 | CG_LITTLE_ENDIAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .compat = "fsl,p2041-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .guts_compat = "fsl,qoriq-device-config-1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .init_periph = p2041_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) &p2041_cmux_grp1, &p2041_cmux_grp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 0, 0, 1, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .pll_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .compat = "fsl,p3041-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .guts_compat = "fsl,qoriq-device-config-1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .init_periph = p2041_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) &p2041_cmux_grp1, &p2041_cmux_grp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 0, 0, 1, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .pll_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .compat = "fsl,p4080-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .guts_compat = "fsl,qoriq-device-config-1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .init_periph = p4080_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) &p4080_cmux_grp1, &p4080_cmux_grp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 0, 0, 0, 0, 1, 1, 1, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .pll_mask = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .compat = "fsl,p5020-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .guts_compat = "fsl,qoriq-device-config-1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .init_periph = p5020_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) &p5020_cmux_grp1, &p5020_cmux_grp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 0, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .pll_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .compat = "fsl,p5040-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .guts_compat = "fsl,p5040-device-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .init_periph = p5040_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) &p5040_cmux_grp1, &p5040_cmux_grp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 0, 0, 1, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .pll_mask = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .compat = "fsl,t1023-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .guts_compat = "fsl,t1023-device-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .init_periph = t1023_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) &t1023_cmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .hwaccel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) &t1023_hwa1, &t1023_hwa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 0, 0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .pll_mask = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .flags = CG_PLL_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .compat = "fsl,t1040-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .guts_compat = "fsl,t1040-device-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .init_periph = t1040_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) &t1040_cmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 0, 0, 0, 0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .pll_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .flags = CG_PLL_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .compat = "fsl,t2080-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .guts_compat = "fsl,t2080-device-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .init_periph = t2080_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) &clockgen2_cmux_cga12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .hwaccel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) &t2080_hwa1, &t2080_hwa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 0, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .pll_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .flags = CG_PLL_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .compat = "fsl,t4240-clockgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .guts_compat = "fsl,t4240-device-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .init_periph = t4240_init_periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .cmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) &clockgen2_cmux_cga, &clockgen2_cmux_cgb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .hwaccel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .cmux_to_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 0, 0, 1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .pll_mask = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .flags = CG_PLL_8BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct mux_hwclock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct clockgen *cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) const struct clockgen_muxinfo *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u8 parent_to_clksel[NUM_MUX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) s8 clksel_to_parent[NUM_MUX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define CLKSEL_MASK 0x78000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define CLKSEL_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int mux_set_parent(struct clk_hw *hw, u8 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct mux_hwclock *hwc = to_mux_hwclock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (idx >= hwc->num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) clksel = hwc->parent_to_clksel[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static u8 mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct mux_hwclock *hwc = to_mux_hwclock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u32 clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) s8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = hwc->clksel_to_parent[clksel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct clk_ops cmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .get_parent = mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .set_parent = mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Don't allow setting for now, as the clock options haven't been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * sanitized for additional restrictions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const struct clk_ops hwaccel_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .get_parent = mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct mux_hwclock *hwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int pll, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) pll = hwc->info->clksel[idx].pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) div = hwc->info->clksel[idx].div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return &cg->pll[pll].div[div];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static struct clk * __init create_mux_common(struct clockgen *cg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct mux_hwclock *hwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) const struct clk_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) unsigned long min_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) unsigned long max_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) unsigned long pct80_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) const char *fmt, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) const struct clockgen_pll_div *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) const char *parent_names[NUM_MUX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) snprintf(name, sizeof(name), fmt, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) hwc->clksel_to_parent[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) div = get_pll_div(cg, hwc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) rate = clk_get_rate(div->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) rate > pct80_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (rate < min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (rate > max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) parent_names[j] = div->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) hwc->parent_to_clksel[j] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) hwc->clksel_to_parent[i] = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) init.num_parents = hwc->num_parents = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) hwc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) hwc->cg = cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) clk = clk_register(NULL, &hwc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) kfree(hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct mux_hwclock *hwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) const struct clockgen_pll_div *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) unsigned long plat_rate, min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) u64 max_rate, pct80_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) u32 clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (!hwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (cg->info.flags & CG_VER3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) hwc->reg = cg->regs + 0x20 * idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * Find the rate for the default clksel, and treat it as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * maximum rated core frequency. If this is an incorrect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * assumption, certain clock options (possibly including the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * default clksel) may be inappropriately excluded on certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) div = get_pll_div(cg, hwc, clksel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (!div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) kfree(hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) max_rate = clk_get_rate(div->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) pct80_rate = max_rate * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) do_div(pct80_rate, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (cg->info.flags & CG_CMUX_GE_PLAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) min_rate = plat_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) min_rate = plat_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) pct80_rate, "cg-cmux%d", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct mux_hwclock *hwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!hwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) hwc->reg = cg->regs + 0x20 * idx + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) hwc->info = cg->info.hwaccel[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) "cg-hwaccel%d", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void __init create_muxes(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (cg->info.cmux_to_group[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (cg->info.cmux_to_group[i] >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ARRAY_SIZE(cg->info.cmux_groups)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) cg->cmux[i] = create_one_cmux(cg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (!cg->info.hwaccel[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) cg->hwaccel[i] = create_one_hwaccel(cg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static void __init _clockgen_init(struct device_node *np, bool legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * Legacy nodes may get probed before the parent clockgen node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * It is assumed that device trees with legacy nodes will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * contain a "clocks" property -- otherwise the input clocks may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * not be initialized at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static void __init legacy_init_clockgen(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (!clockgen.node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) _clockgen_init(of_get_parent(np), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* Legacy node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static void __init core_mux_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) int idx, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) legacy_init_clockgen(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (of_address_to_resource(np, 0, &res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) idx = (res.start & 0xf0) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) clk = clockgen.cmux[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) __func__, np, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static struct clk __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) *sysclk_from_fixed(struct device_node *node, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (of_property_read_u32(node, "clock-frequency", &rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static struct clk __init *input_clock(const char *name, struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) const char *input_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* Register the input clock under the desired name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) input_name = __clk_get_name(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) clk = clk_register_fixed_factor(NULL, name, input_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static struct clk __init *input_clock_by_name(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) const char *dtname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) clk = of_clk_get_by_name(clockgen.node, dtname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return input_clock(name, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static struct clk __init *input_clock_by_index(const char *name, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) clk = of_clk_get(clockgen.node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return input_clock(name, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static struct clk * __init create_sysclk(const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct device_node *sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) clk = sysclk_from_fixed(clockgen.node, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) clk = input_clock_by_name(name, "sysclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) clk = input_clock_by_index(name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) sysclk = of_get_child_by_name(clockgen.node, "sysclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (sysclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) clk = sysclk_from_fixed(sysclk, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) pr_err("%s: No input sysclk\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static struct clk * __init create_coreclk(const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) clk = input_clock_by_name(name, "coreclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * This indicates a mix of legacy nodes with the new coreclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * mechanism, which should never happen. If this error occurs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * don't use the wrong input clock just because coreclk isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * ready yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Legacy node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static void __init sysclk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) legacy_init_clockgen(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) clk = clockgen.sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define PLL_KILL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static void __init create_one_pll(struct clockgen *cg, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) u32 __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) u32 mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct clockgen_pll *pll = &cg->pll[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) const char *input = "cg-sysclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (!(cg->info.pll_mask & (1 << idx)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (cg->coreclk && idx != PLATFORM_PLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (IS_ERR(cg->coreclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) input = "cg-coreclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (cg->info.flags & CG_VER3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) switch (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) case PLATFORM_PLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) reg = cg->regs + 0x60080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) case CGA_PLL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) reg = cg->regs + 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) case CGA_PLL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) reg = cg->regs + 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) case CGB_PLL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) reg = cg->regs + 0x10080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) case CGB_PLL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) reg = cg->regs + 0x100a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) WARN_ONCE(1, "index %d\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (idx == PLATFORM_PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) reg = cg->regs + 0xc00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) reg = cg->regs + 0x800 + 0x20 * (idx - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* Get the multiple of PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) mult = cg_in(cg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* Check if this PLL is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (mult & PLL_KILL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) pr_debug("%s(): pll %p disabled\n", __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if ((cg->info.flags & CG_VER3) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) mult = (mult & GENMASK(8, 1)) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) mult = (mult & GENMASK(6, 1)) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * For platform PLL, there are MAX_PLL_DIV divider clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * For core PLL, there are 4 divider clocks at most.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (idx != PLATFORM_PLL && i >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) snprintf(pll->div[i].name, sizeof(pll->div[i].name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) "cg-pll%d-div%d", idx, i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) clk = clk_register_fixed_factor(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) pll->div[i].name, input, 0, mult, i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) pr_err("%s: %s: register failed %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) __func__, pll->div[i].name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) pll->div[i].clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) pr_err("%s: %s: register to lookup table failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) __func__, pll->div[i].name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static void __init create_plls(struct clockgen *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) create_one_pll(cg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static void __init legacy_pll_init(struct device_node *np, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct clockgen_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct clk_onecell_data *onecell_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct clk **subclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) int count, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) legacy_init_clockgen(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) pll = &clockgen.pll[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) count = of_property_count_strings(np, "clock-output-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!subclks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (!onecell_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) goto err_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (count <= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) subclks[0] = pll->div[0].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) subclks[1] = pll->div[1].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) subclks[2] = pll->div[3].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) subclks[0] = pll->div[0].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) subclks[1] = pll->div[1].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) subclks[2] = pll->div[2].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) subclks[3] = pll->div[3].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) onecell_data->clks = subclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) onecell_data->clk_num = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) __func__, np, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) goto err_cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) err_cell:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) kfree(onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) err_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) kfree(subclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* Legacy node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static void __init pltfrm_pll_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) legacy_pll_init(np, PLATFORM_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* Legacy node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static void __init core_pll_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (of_address_to_resource(np, 0, &res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if ((res.start & 0xfff) == 0xc00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * ls1021a devtree labels the platform PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * with the core PLL compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) pltfrm_pll_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) idx = (res.start & 0xf0) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) legacy_pll_init(np, CGA_PLL1 + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct clockgen *cg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct clockgen_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) u32 type, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (clkspec->args_count < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) pr_err("%s: insufficient phandle args\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) type = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) idx = clkspec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (idx != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) goto bad_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) clk = cg->sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (idx >= ARRAY_SIZE(cg->cmux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) goto bad_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) clk = cg->cmux[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (idx >= ARRAY_SIZE(cg->hwaccel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) goto bad_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) clk = cg->hwaccel[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (idx >= ARRAY_SIZE(cg->fman))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) goto bad_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) clk = cg->fman[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) pll = &cg->pll[PLATFORM_PLL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (idx >= ARRAY_SIZE(pll->div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) goto bad_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) clk = pll->div[idx].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (idx != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) goto bad_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) clk = cg->coreclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) goto bad_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) bad_args:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #ifdef CONFIG_PPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #include <asm/mpc85xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static const u32 a4510_svrs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define SVR_SECURITY 0x80000 /* The Security (E) bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static bool __init has_erratum_a4510(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u32 svr = mfspr(SPRN_SVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) svr &= ~SVR_SECURITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (svr == a4510_svrs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static bool __init has_erratum_a4510(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static void __init _clockgen_init(struct device_node *np, bool legacy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) bool is_old_ls1021a = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* May have already been called by a legacy probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (clockgen.node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) clockgen.node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) clockgen.regs = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (!clockgen.regs &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) of_device_is_compatible(of_root, "fsl,ls1021a")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* Compatibility hack for old, broken device trees */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) clockgen.regs = ioremap(0x1ee1000, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) is_old_ls1021a = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (!clockgen.regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (of_device_is_compatible(np, chipinfo[i].compat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (is_old_ls1021a &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (i == ARRAY_SIZE(chipinfo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) clockgen.info = chipinfo[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (clockgen.info.guts_compat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct device_node *guts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) guts = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) clockgen.info.guts_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (guts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) clockgen.guts = of_iomap(guts, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (!clockgen.guts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) pr_err("%s: Couldn't map %pOF regs\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) guts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) of_node_put(guts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (has_erratum_a4510())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) clockgen.info.flags |= CG_CMUX_GE_PLAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) clockgen.sysclk = create_sysclk("cg-sysclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) clockgen.coreclk = create_coreclk("cg-coreclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) create_plls(&clockgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) create_muxes(&clockgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (clockgen.info.init_periph)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) clockgen.info.init_periph(&clockgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) __func__, np, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* Don't create cpufreq device for legacy clockgen blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) add_cpufreq_dev = !legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) iounmap(clockgen.regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) clockgen.regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static void __init clockgen_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) _clockgen_init(np, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static int __init clockgen_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (add_cpufreq_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) pdev = platform_device_register_simple("qoriq-cpufreq", -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (IS_ERR(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pr_err("Couldn't register qoriq-cpufreq err=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) PTR_ERR(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) device_initcall(clockgen_cpufreq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* Legacy nodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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