^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Philipp Zabel, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * PWM (mis)used as clock output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct clk_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct pwm_device *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static inline struct clk_pwm *to_clk_pwm(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) return container_of(hw, struct clk_pwm, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int clk_pwm_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_pwm *clk_pwm = to_clk_pwm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return pwm_enable(clk_pwm->pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void clk_pwm_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk_pwm *clk_pwm = to_clk_pwm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pwm_disable(clk_pwm->pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static unsigned long clk_pwm_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk_pwm *clk_pwm = to_clk_pwm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return clk_pwm->fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int clk_pwm_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_pwm *clk_pwm = to_clk_pwm(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct pwm_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pwm_get_state(clk_pwm->pwm, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) duty->num = state.duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) duty->den = state.period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct clk_ops clk_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .prepare = clk_pwm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .unprepare = clk_pwm_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .recalc_rate = clk_pwm_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .get_duty_cycle = clk_pwm_get_duty_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int clk_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk_pwm *clk_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct pwm_device *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct pwm_args pargs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clk_pwm = devm_kzalloc(&pdev->dev, sizeof(*clk_pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!clk_pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pwm = devm_pwm_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (IS_ERR(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return PTR_ERR(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pwm_get_args(pwm, &pargs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!pargs.period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_err(&pdev->dev, "invalid PWM period\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!clk_pwm->fixed_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_err(&pdev->dev, "fixed_rate cannot be zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "clock-frequency does not match PWM period\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * FIXME: pwm_apply_args() should be removed when switching to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * atomic PWM API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pwm_apply_args(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = pwm_config(pwm, (pargs.period + 1) >> 1, pargs.period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) init.ops = &clk_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk_pwm->pwm = pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clk_pwm->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = devm_clk_hw_register(&pdev->dev, &clk_pwm->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clk_pwm->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int clk_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct of_device_id clk_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .compatible = "pwm-clock" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MODULE_DEVICE_TABLE(of, clk_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct platform_driver clk_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .probe = clk_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .remove = clk_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .name = "pwm-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .of_match_table = of_match_ptr(clk_pwm_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) module_platform_driver(clk_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MODULE_DESCRIPTION("PWM clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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