^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* PLLDIG register offsets and bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLLDIG_REG_PLLSR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLLDIG_LOCK_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLLDIG_REG_PLLDV 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLLDIG_MFD_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLLDIG_RFDPHI1_MASK GENMASK(30, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLLDIG_REG_PLLFM 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLLDIG_SSCGBYP_ENABLE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLLDIG_REG_PLLFD 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLLDIG_FDEN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLLDIG_FRAC_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLLDIG_REG_PLLCAL1 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PLLDIG_REG_PLLCAL2 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Range of the VCO frequencies, in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLLDIG_MIN_VCO_FREQ 650000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLLDIG_MAX_VCO_FREQ 1300000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Range of the output frequencies, in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PHI1_MIN_FREQ 27000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHI1_MAX_FREQ 600000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Maximum value of the reduced frequency divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAX_RFDPHI1 63UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Best value of multiplication factor divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PLLDIG_DEFAULT_MFD 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Denominator part of the fractional part of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * loop multiplication factor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MFDEN 20480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct clk_parent_data parent_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .index = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk_plldig {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int plldig_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clk_plldig *data = to_clk_plldig(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val = readl(data->regs + PLLDIG_REG_PLLFM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Use Bypass mode with PLL off by default, the frequency overshoot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * detector output was disable. SSCG Bypass mode should be enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val |= PLLDIG_SSCGBYP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(val, data->regs + PLLDIG_REG_PLLFM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void plldig_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct clk_plldig *data = to_clk_plldig(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val = readl(data->regs + PLLDIG_REG_PLLFM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val &= ~PLLDIG_SSCGBYP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) val |= FIELD_PREP(PLLDIG_SSCGBYP_ENABLE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(val, data->regs + PLLDIG_REG_PLLFM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int plldig_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk_plldig *data = to_clk_plldig(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return readl(data->regs + PLLDIG_REG_PLLFM) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PLLDIG_SSCGBYP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static unsigned long plldig_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk_plldig *data = to_clk_plldig(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val, rfdphi1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val = readl(data->regs + PLLDIG_REG_PLLDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Check if PLL is bypassed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (val & PLLDIG_SSCGBYP_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rfdphi1 = FIELD_GET(PLLDIG_RFDPHI1_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * If RFDPHI1 has a value of 1 the VCO frequency is also divided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!rfdphi1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rfdphi1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return DIV_ROUND_UP(data->vco_freq, rfdphi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static unsigned long plldig_calc_target_div(unsigned long vco_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long target_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) div = DIV_ROUND_CLOSEST(vco_freq, target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) div = clamp(div, 1UL, MAX_RFDPHI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int plldig_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk_plldig *data = to_clk_plldig(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) req->rate = clamp(req->rate, PHI1_MIN_FREQ, PHI1_MAX_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) div = plldig_calc_target_div(data->vco_freq, req->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) req->rate = DIV_ROUND_UP(data->vco_freq, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int plldig_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct clk_plldig *data = to_clk_plldig(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int val, cond;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int rfdphi1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rate = clamp(rate, PHI1_MIN_FREQ, PHI1_MAX_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rfdphi1 = plldig_calc_target_div(data->vco_freq, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* update the divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val = readl(data->regs + PLLDIG_REG_PLLDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) val &= ~PLLDIG_RFDPHI1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) val |= FIELD_PREP(PLLDIG_RFDPHI1_MASK, rfdphi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel(val, data->regs + PLLDIG_REG_PLLDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* waiting for old lock state to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Wait until PLL is locked or timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cond & PLLDIG_LOCK_MASK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) USEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct clk_ops plldig_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .enable = plldig_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .disable = plldig_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .is_enabled = plldig_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .recalc_rate = plldig_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .determine_rate = plldig_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .set_rate = plldig_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int plldig_init(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct clk_plldig *data = to_clk_plldig(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk_hw *parent = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long long lltmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int mfd, fracdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (data->vco_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mfd = data->vco_freq / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) lltmp = data->vco_freq % parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) lltmp *= MFDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) do_div(lltmp, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) fracdiv = lltmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mfd = PLLDIG_DEFAULT_MFD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) data->vco_freq = parent_rate * mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val = FIELD_PREP(PLLDIG_MFD_MASK, mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) writel(val, data->regs + PLLDIG_REG_PLLDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Enable fractional divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (fracdiv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val = FIELD_PREP(PLLDIG_FRAC_MASK, fracdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val |= PLLDIG_FDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(val, data->regs + PLLDIG_REG_PLLFD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int plldig_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct clk_plldig *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) data->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (IS_ERR(data->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return PTR_ERR(data->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &plldig_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = devm_clk_hw_register(dev, &data->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(dev, "failed to register %s clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev->of_node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) &data->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(dev, "unable to add clk provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * The frequency of the VCO cannot be changed during runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Therefore, let the user specify a desired frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!of_property_read_u32(dev->of_node, "fsl,vco-hz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) &data->vco_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (data->vco_freq < PLLDIG_MIN_VCO_FREQ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) data->vco_freq > PLLDIG_MAX_VCO_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return plldig_init(&data->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct of_device_id plldig_clk_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .compatible = "fsl,ls1028a-plldig" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MODULE_DEVICE_TABLE(of, plldig_clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct platform_driver plldig_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .name = "plldig-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .of_match_table = plldig_clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .probe = plldig_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) module_platform_driver(plldig_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MODULE_AUTHOR("Wen He <wen.he_1@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_DESCRIPTION("LS1028A Display output interface pixel clock driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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