^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Clock driver for Palmas device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013-2014 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * whether express or implied; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/palmas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct palmas_clk32k_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int sleep_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int sleep_reqstr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct palmas_clock_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct palmas *palmas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct palmas_clk32k_desc *clk_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ext_control_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline struct palmas_clock_info *to_palmas_clks_info(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return container_of(hw, struct palmas_clock_info, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static unsigned long palmas_clks_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int palmas_clks_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cinfo->clk_desc->control_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cinfo->clk_desc->enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cinfo->clk_desc->enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cinfo->clk_desc->control_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else if (cinfo->clk_desc->delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) udelay(cinfo->clk_desc->delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void palmas_clks_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Clock can be disabled through external pin if it is externally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * controlled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (cinfo->ext_control_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cinfo->clk_desc->control_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) cinfo->clk_desc->enable_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) cinfo->clk_desc->control_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int palmas_clks_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (cinfo->ext_control_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = palmas_read(cinfo->palmas, PALMAS_RESOURCE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cinfo->clk_desc->control_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev_err(cinfo->dev, "Reg 0x%02x read failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cinfo->clk_desc->control_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return !!(val & cinfo->clk_desc->enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct clk_ops palmas_clks_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .prepare = palmas_clks_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .unprepare = palmas_clks_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .is_prepared = palmas_clks_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .recalc_rate = palmas_clks_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct palmas_clks_of_match_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct palmas_clk32k_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct palmas_clks_of_match_data palmas_of_clk32kg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "clk32kg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .ops = &palmas_clks_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .clk_name = "clk32kg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .control_reg = PALMAS_CLK32KG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .delay = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct palmas_clks_of_match_data palmas_of_clk32kgaudio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "clk32kgaudio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .ops = &palmas_clks_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .clk_name = "clk32kgaudio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .delay = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct of_device_id palmas_clks_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .compatible = "ti,palmas-clk32kg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .data = &palmas_of_clk32kg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .compatible = "ti,palmas-clk32kgaudio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .data = &palmas_of_clk32kgaudio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_DEVICE_TABLE(of, palmas_clks_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void palmas_clks_get_clk_data(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct palmas_clock_info *cinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = of_property_read_u32(node, "ti,external-sleep-control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) switch (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) prop = PALMAS_EXT_CONTROL_ENABLE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) prop = PALMAS_EXT_CONTROL_ENABLE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) prop = PALMAS_EXT_CONTROL_NSLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_warn(&pdev->dev, "%pOFn: Invalid ext control option: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) node, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) prop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cinfo->ext_control_pin = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int palmas_clks_init_configure(struct palmas_clock_info *cinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cinfo->clk_desc->control_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cinfo->clk_desc->sleep_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cinfo->clk_desc->control_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (cinfo->ext_control_pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = clk_prepare(cinfo->hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_err(cinfo->dev, "Clock prep failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = palmas_ext_control_req_config(cinfo->palmas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) cinfo->clk_desc->sleep_reqstr_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cinfo->ext_control_pin, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(cinfo->dev, "Ext config for %s failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cinfo->clk_desc->clk_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clk_unprepare(cinfo->hw.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int palmas_clks_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const struct palmas_clks_of_match_data *match_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct palmas_clock_info *cinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) match_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!match_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!cinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) palmas_clks_get_clk_data(pdev, cinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) platform_set_drvdata(pdev, cinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cinfo->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) cinfo->palmas = palmas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cinfo->clk_desc = &match_data->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cinfo->hw.init = &match_data->init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = devm_clk_hw_register(&pdev->dev, &cinfo->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_err(&pdev->dev, "Fail to register clock %s, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) match_data->desc.clk_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = palmas_clks_init_configure(cinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_err(&pdev->dev, "Clock config failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &cinfo->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_err(&pdev->dev, "Fail to add clock driver, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int palmas_clks_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct platform_driver palmas_clks_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "palmas-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .of_match_table = palmas_clks_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .probe = palmas_clks_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .remove = palmas_clks_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) module_platform_driver(palmas_clks_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_DESCRIPTION("Clock driver for Palmas Series Devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_ALIAS("platform:palmas-clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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