^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Stephen Warren
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/stringify.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/oxsemi,ox810se.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/oxsemi,ox820.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Standard regmap gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_oxnas_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct oxnas_stdclk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk_hw_onecell_data *onecell_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk_oxnas_gate **gates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int ngates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk_oxnas_pll **plls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int nplls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Regmap offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_STAT_REGOFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_SET_REGOFFSET 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_CLR_REGOFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return container_of(hw, struct clk_oxnas_gate, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int oxnas_clk_gate_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return val & BIT(std->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int oxnas_clk_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void oxnas_clk_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct clk_ops oxnas_clk_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .enable = oxnas_clk_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .disable = oxnas_clk_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .is_enabled = oxnas_clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const char *const osc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "oscillator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const char *const eth_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "gmacclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OXNAS_GATE(_name, _bit, _parents) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct clk_oxnas_gate _name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .bit = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .ops = &oxnas_clk_gate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .parent_names = _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .num_parents = ARRAY_SIZE(_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static OXNAS_GATE(ox810se_leon, 0, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static OXNAS_GATE(ox810se_cipher, 2, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static OXNAS_GATE(ox810se_sata, 4, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static OXNAS_GATE(ox810se_audio, 5, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static OXNAS_GATE(ox810se_usbmph, 6, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static OXNAS_GATE(ox810se_etha, 7, eth_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static OXNAS_GATE(ox810se_pciea, 8, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static OXNAS_GATE(ox810se_nand, 9, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct clk_oxnas_gate *ox810se_gates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) &ox810se_leon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) &ox810se_dma_sgdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) &ox810se_cipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) &ox810se_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) &ox810se_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) &ox810se_usbmph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) &ox810se_etha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) &ox810se_pciea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) &ox810se_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static OXNAS_GATE(ox820_leon, 0, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static OXNAS_GATE(ox820_dma_sgdma, 1, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static OXNAS_GATE(ox820_cipher, 2, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static OXNAS_GATE(ox820_sd, 3, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static OXNAS_GATE(ox820_sata, 4, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static OXNAS_GATE(ox820_audio, 5, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static OXNAS_GATE(ox820_usbmph, 6, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static OXNAS_GATE(ox820_etha, 7, eth_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static OXNAS_GATE(ox820_pciea, 8, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static OXNAS_GATE(ox820_nand, 9, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static OXNAS_GATE(ox820_ethb, 10, eth_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static OXNAS_GATE(ox820_pcieb, 11, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static OXNAS_GATE(ox820_ref600, 12, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static OXNAS_GATE(ox820_usbdev, 13, osc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct clk_oxnas_gate *ox820_gates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &ox820_leon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) &ox820_dma_sgdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) &ox820_cipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) &ox820_sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) &ox820_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &ox820_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &ox820_usbmph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &ox820_etha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) &ox820_pciea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &ox820_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) &ox820_etha,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) &ox820_pciea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) &ox820_ref600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) &ox820_usbdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct clk_hw_onecell_data ox810se_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [CLK_810_LEON] = &ox810se_leon.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [CLK_810_DMA_SGDMA] = &ox810se_dma_sgdma.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [CLK_810_CIPHER] = &ox810se_cipher.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [CLK_810_SATA] = &ox810se_sata.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [CLK_810_AUDIO] = &ox810se_audio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [CLK_810_USBMPH] = &ox810se_usbmph.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [CLK_810_ETHA] = &ox810se_etha.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [CLK_810_PCIEA] = &ox810se_pciea.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [CLK_810_NAND] = &ox810se_nand.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .num = ARRAY_SIZE(ox810se_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct clk_hw_onecell_data ox820_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [CLK_820_LEON] = &ox820_leon.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [CLK_820_DMA_SGDMA] = &ox820_dma_sgdma.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [CLK_820_CIPHER] = &ox820_cipher.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [CLK_820_SD] = &ox820_sd.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [CLK_820_SATA] = &ox820_sata.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [CLK_820_AUDIO] = &ox820_audio.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [CLK_820_USBMPH] = &ox820_usbmph.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [CLK_820_ETHA] = &ox820_etha.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [CLK_820_PCIEA] = &ox820_pciea.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [CLK_820_NAND] = &ox820_nand.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [CLK_820_ETHB] = &ox820_ethb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [CLK_820_PCIEB] = &ox820_pcieb.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [CLK_820_REF600] = &ox820_ref600.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [CLK_820_USBDEV] = &ox820_usbdev.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .num = ARRAY_SIZE(ox820_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct oxnas_stdclk_data ox810se_stdclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .onecell_data = &ox810se_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .gates = ox810se_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .ngates = ARRAY_SIZE(ox810se_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct oxnas_stdclk_data ox820_stdclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .onecell_data = &ox820_hw_onecell_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .gates = ox820_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .ngates = ARRAY_SIZE(ox820_gates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct of_device_id oxnas_stdclk_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .compatible = "oxsemi,ox820-stdclk", &ox820_stdclk_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int oxnas_stdclk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const struct oxnas_stdclk_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) id = of_match_device(oxnas_stdclk_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) data = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(&pdev->dev, "failed to have parent regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) for (i = 0 ; i < data->ngates ; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) data->gates[i]->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 0; i < data->onecell_data->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!data->onecell_data->hws[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = devm_clk_hw_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) data->onecell_data->hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) data->onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct platform_driver oxnas_stdclk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .probe = oxnas_stdclk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "oxnas-stdclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .of_match_table = oxnas_stdclk_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) builtin_platform_driver(oxnas_stdclk_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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