^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MHZ (1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BASE_CPU_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BASE_CPU_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CPU_AHB_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CPU_AHB_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FIXED_BASE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FIXED_BASE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLASSIC_BASE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLASSIC_BASE_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CX_BASE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CX_BASE_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CX_UNKNOWN_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CX_UNKNOWN_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct nspire_clk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 base_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u16 base_cpu_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u16 base_ahb_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EXTRACT(var, prop) (((var)>>prop##_SHIFT) & prop##_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (EXTRACT(val, FIXED_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) clk->base_clock = 48 * MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (EXTRACT(val, FIXED_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clk->base_clock = 27 * MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void __init nspire_ahbdiv_setup(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void (*get_clkinfo)(u32, struct nspire_clk_info *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct nspire_clk_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) io = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val = readl(io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) iounmap(io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) get_clkinfo(val, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) hw = clk_hw_register_fixed_factor(NULL, clk_name, parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 1, info.base_ahb_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void __init nspire_ahbdiv_setup_cx(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) nspire_ahbdiv_setup(node, nspire_clkinfo_cx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void __init nspire_ahbdiv_setup_classic(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) nspire_ahbdiv_setup(node, nspire_clkinfo_classic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CLK_OF_DECLARE(nspire_ahbdiv_cx, "lsi,nspire-cx-ahb-divider",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) nspire_ahbdiv_setup_cx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) CLK_OF_DECLARE(nspire_ahbdiv_classic, "lsi,nspire-classic-ahb-divider",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) nspire_ahbdiv_setup_classic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void __init nspire_clk_setup(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void (*get_clkinfo)(u32, struct nspire_clk_info *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct nspire_clk_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) io = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val = readl(io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) iounmap(io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) get_clkinfo(val, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) hw = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) info.base_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pr_info("TI-NSPIRE Base: %uMHz CPU: %uMHz AHB: %uMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) info.base_clock / MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) info.base_clock / info.base_cpu_ratio / MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) info.base_clock / info.base_ahb_ratio / MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void __init nspire_clk_setup_cx(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) nspire_clk_setup(node, nspire_clkinfo_cx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void __init nspire_clk_setup_classic(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) nspire_clk_setup(node, nspire_clkinfo_classic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_OF_DECLARE(nspire_clk_cx, "lsi,nspire-cx-clock", nspire_clk_setup_cx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CLK_OF_DECLARE(nspire_clk_classic, "lsi,nspire-classic-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) nspire_clk_setup_classic);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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