^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Nuvoton NPCM7xx Clock Generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All the clocks are initialized by the bootloader, so this driver allow only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * reading of current settings directly from the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct npcm7xx_clk_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void __iomem *pllcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLLCON_LOKI BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLLCON_LOKS BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLLCON_FBDV GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PLLCON_OTDV2 GENMASK(15, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PLLCON_PWDEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLLCON_OTDV1 GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLLCON_INDV GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long fbdv, indv, otdv1, otdv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u64 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (parent_rate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pr_err("%s: parent rate is zero", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) val = readl_relaxed(pll->pllcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) indv = FIELD_GET(PLLCON_INDV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) fbdv = FIELD_GET(PLLCON_FBDV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) otdv1 = FIELD_GET(PLLCON_OTDV1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) otdv2 = FIELD_GET(PLLCON_OTDV2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ret = (u64)parent_rate * fbdv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) do_div(ret, indv * otdv1 * otdv2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct clk_ops npcm7xx_clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .recalc_rate = npcm7xx_clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const char *parent_name, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct npcm7xx_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) init.ops = &npcm7xx_clk_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pll->pllcon = pllcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) hw = &pll->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NPCM7XX_CLKEN1 (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define NPCM7XX_CLKEN2 (0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NPCM7XX_CLKEN3 (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NPCM7XX_CLKSEL (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define NPCM7XX_CLKDIV1 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define NPCM7XX_CLKDIV2 (0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define NPCM7XX_CLKDIV3 (0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NPCM7XX_PLLCON0 (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NPCM7XX_PLLCON1 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NPCM7XX_PLLCON2 (0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NPCM7XX_SWRSTR (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NPCM7XX_IRQWAKECON (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define NPCM7XX_IRQWAKEFLAG (0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define NPCM7XX_IPSRST1 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NPCM7XX_IPSRST2 (0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define NPCM7XX_IPSRST3 (0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define NPCM7XX_WD0RCR (0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define NPCM7XX_WD1RCR (0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define NPCM7XX_WD2RCR (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NPCM7XX_SWRSTC1 (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NPCM7XX_SWRSTC2 (0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define NPCM7XX_SWRSTC3 (0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define NPCM7XX_SWRSTC4 (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define NPCM7XX_CORSTC (0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define NPCM7XX_PLLCONG (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define NPCM7XX_AHBCKFI (0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define NPCM7XX_SECCNT (0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define NPCM7XX_CNTR25M (0x6C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct npcm7xx_clk_gate_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * If this clock is exported via DT, set onecell_idx to constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * this specific clock. Otherwise, set to -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int onecell_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct npcm7xx_clk_mux_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * If this clock is exported via DT, set onecell_idx to constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * this specific clock. Otherwise, set to -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int onecell_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct npcm7xx_clk_div_fixed_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 clk_divider_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * If this clock is exported via DT, set onecell_idx to constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * this specific clock. Otherwise, set to -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int onecell_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct npcm7xx_clk_div_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 clk_divider_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * If this clock is exported via DT, set onecell_idx to constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * this specific clock. Otherwise, set to -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int onecell_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct npcm7xx_clk_pll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * If this clock is exported via DT, set onecell_idx to constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * this specific clock. Otherwise, set to -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int onecell_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Single copy of strings used to refer to clocks within this driver indexed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * above enum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define NPCM7XX_CLK_S_REFCLK "refclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define NPCM7XX_CLK_S_SYSBYPCK "sysbypck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define NPCM7XX_CLK_S_MCBYPCK "mcbypck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define NPCM7XX_CLK_S_PLL0 "pll0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define NPCM7XX_CLK_S_PLL1 "pll1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define NPCM7XX_CLK_S_PLL2 "pll2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define NPCM7XX_CLK_S_PLL_GFX "pll_gfx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define NPCM7XX_CLK_S_MC_MUX "mc_phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define NPCM7XX_CLK_S_MC "mc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define NPCM7XX_CLK_S_UART_MUX "uart_mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define NPCM7XX_CLK_S_TIM_MUX "timer_mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define NPCM7XX_CLK_S_SD_MUX "sd_mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define NPCM7XX_CLK_S_DVC_MUX "dvc_mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define NPCM7XX_CLK_S_GFX_MUX "gfx_mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define NPCM7XX_CLK_S_SPI0 "spi0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define NPCM7XX_CLK_S_SPI3 "spi3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define NPCM7XX_CLK_S_SPIX "spix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define NPCM7XX_CLK_S_APB1 "apb1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define NPCM7XX_CLK_S_APB2 "apb2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define NPCM7XX_CLK_S_APB3 "apb3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define NPCM7XX_CLK_S_APB4 "apb4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define NPCM7XX_CLK_S_APB5 "apb5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define NPCM7XX_CLK_S_TOCK "tock"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define NPCM7XX_CLK_S_CLKOUT "clkout"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define NPCM7XX_CLK_S_UART "uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define NPCM7XX_CLK_S_TIMER "timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define NPCM7XX_CLK_S_MMC "mmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define NPCM7XX_CLK_S_SDHC "sdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define NPCM7XX_CLK_S_ADC "adc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define NPCM7XX_CLK_S_USBIF "serial_usbif"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define NPCM7XX_CLK_S_USB_HOST "usb_host"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define NPCM7XX_CLK_S_PCI "pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static u32 pll_mux_table[] = {0, 1, 2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const char * const pll_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) NPCM7XX_CLK_S_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) NPCM7XX_CLK_S_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) NPCM7XX_CLK_S_REFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) NPCM7XX_CLK_S_PLL2_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static u32 cpuck_mux_table[] = {0, 1, 2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const char * const cpuck_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) NPCM7XX_CLK_S_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) NPCM7XX_CLK_S_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) NPCM7XX_CLK_S_REFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) NPCM7XX_CLK_S_SYSBYPCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static u32 pixcksel_mux_table[] = {0, 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const char * const pixcksel_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) NPCM7XX_CLK_S_PLL_GFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) NPCM7XX_CLK_S_REFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static u32 sucksel_mux_table[] = {2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const char * const sucksel_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) NPCM7XX_CLK_S_REFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) NPCM7XX_CLK_S_PLL2_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static u32 mccksel_mux_table[] = {0, 2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const char * const mccksel_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) NPCM7XX_CLK_S_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) NPCM7XX_CLK_S_REFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) NPCM7XX_CLK_S_MCBYPCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const char * const clkoutsel_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) NPCM7XX_CLK_S_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) NPCM7XX_CLK_S_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) NPCM7XX_CLK_S_REFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) NPCM7XX_CLK_S_PLL_GFX, // divided by 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) NPCM7XX_CLK_S_PLL2_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static u32 gfxmsel_mux_table[] = {2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const char * const gfxmsel_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) NPCM7XX_CLK_S_REFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) NPCM7XX_CLK_S_PLL2_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static u32 dvcssel_mux_table[] = {2, 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const char * const dvcssel_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) NPCM7XX_CLK_S_REFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) NPCM7XX_CLK_S_PLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) NPCM7XX_CLK_S_REFCLK, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) NPCM7XX_CLK_S_REFCLK, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) NPCM7XX_CLK_S_REFCLK, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) NPCM7XX_CLK_CPU},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) NPCM7XX_CLK_GFX_PIXEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* fixed ratio dividers (no register): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* configurable dividers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*30-28 ADCCKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*27-26 CLK4DIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*25-21 TIMCKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*20-16 UARTDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*15-11 MMCCKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*10-6 AHB3CKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*5-2 PCICKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) NPCM7XX_CLK_AXI},/*0 CLK2DIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*31-30 APB4CKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*29-28 APB3CKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*27-26 APB2CKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*25-24 APB1CKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*23-22 APB5CKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*20-16 CLKOUTDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*15-13 GFXCKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /*12-8 SUCKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*7-4 SU48CKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ,/*3-0 SD1CKDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*10-6 SPI0CKDV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*5-1 SPIXCKDV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* bit 3 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* bit 29 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* bit 24 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* bit 20 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* bit 17 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* bit 15 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* bit 11 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* bit 10 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* bit 8 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static DEFINE_SPINLOCK(npcm7xx_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void __init npcm7xx_clk_init(struct device_node *clk_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct clk_hw_onecell_data *npcm7xx_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = of_address_to_resource(clk_np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pr_err("%pOFn: failed to get resource, ret %d\n", clk_np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) clk_base = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!clk_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto npcm7xx_init_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) npcm7xx_clk_data = kzalloc(struct_size(npcm7xx_clk_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) NPCM7XX_NUM_CLOCKS), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!npcm7xx_clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) goto npcm7xx_init_np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Register plls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pll_data->name, pll_data->parent_name, pll_data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pr_err("npcm7xx_clk: Can't register pll\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) goto npcm7xx_init_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (pll_data->onecell_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Register fixed dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) NPCM7XX_CLK_S_PLL1, 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pr_err("npcm7xx_clk: Can't register fixed div\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto npcm7xx_init_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) NPCM7XX_CLK_S_PLL2, 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pr_err("npcm7xx_clk: Can't register div2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) goto npcm7xx_init_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Register muxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) hw = clk_hw_register_mux_table(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mux_data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mux_data->parent_names, mux_data->num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mux_data->flags, clk_base + NPCM7XX_CLKSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mux_data->shift, mux_data->mask, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mux_data->table, &npcm7xx_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pr_err("npcm7xx_clk: Can't register mux\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) goto npcm7xx_init_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (mux_data->onecell_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Register clock dividers specified in npcm7xx_divs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hw = clk_hw_register_divider(NULL, div_data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) div_data->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) div_data->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) clk_base + div_data->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) div_data->shift, div_data->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) div_data->clk_divider_flags, &npcm7xx_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pr_err("npcm7xx_clk: Can't register div table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto npcm7xx_init_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (div_data->onecell_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) npcm7xx_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pr_err("failed to add DT provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) of_node_put(clk_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) npcm7xx_init_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) kfree(npcm7xx_clk_data->hws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) npcm7xx_init_np_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) iounmap(clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) npcm7xx_init_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) of_node_put(clk_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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