^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Simple multiplexer clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * DOC: basic adjustable multiplexer clock that cannot gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * prepare - clk_prepare only ensures that parents are prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * enable - clk_enable only ensures that parents are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * rate - rate is only affected by parent switching. No clk_set_rate support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * parent - parent is adjustable through clk_set_parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline u32 clk_mux_readl(struct clk_mux *mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (mux->flags & CLK_MUX_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return ioread32be(mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return readl(mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (mux->flags & CLK_MUX_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) iowrite32be(val, mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) writel(val, mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) for (i = 0; i < num_parents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (table[i] == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (val && (flags & CLK_MUX_INDEX_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val = ffs(val) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (val && (flags & CLK_MUX_INDEX_ONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (val >= num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) EXPORT_SYMBOL_GPL(clk_mux_val_to_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int val = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val = table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (flags & CLK_MUX_INDEX_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val = 1 << index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (flags & CLK_MUX_INDEX_ONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EXPORT_SYMBOL_GPL(clk_mux_index_to_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static u8 clk_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk_mux *mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val = clk_mux_readl(mux) >> mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val &= mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct clk_mux *mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spin_lock_irqsave(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __acquire(mux->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (mux->flags & CLK_MUX_HIWORD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg = mux->mask << (mux->shift + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg = clk_mux_readl(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg &= ~(mux->mask << mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val = val << mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clk_mux_writel(mux, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) spin_unlock_irqrestore(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __release(mux->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int clk_mux_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct clk_mux *mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return clk_mux_determine_rate_flags(hw, req, mux->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const struct clk_ops clk_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .get_parent = clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .set_parent = clk_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .determine_rate = clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) EXPORT_SYMBOL_GPL(clk_mux_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct clk_ops clk_mux_ro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .get_parent = clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const char *name, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const struct clk_hw **parent_hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const struct clk_parent_data *parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 clk_mux_flags, u32 *table, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) width = fls(mask) - ffs(mask) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (width + shift > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pr_err("mux value exceeds LOWORD field\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* allocate the mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (clk_mux_flags & CLK_MUX_READ_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) init.ops = &clk_mux_ro_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) init.ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) init.parent_data = parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) init.parent_hws = parent_hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* struct clk_mux assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mux->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mux->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mux->mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mux->flags = clk_mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mux->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mux->table = table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (dev || !np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) else if (np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = of_clk_hw_register(np, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EXPORT_SYMBOL_GPL(__clk_hw_register_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct clk *clk_register_mux_table(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const char * const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 clk_mux_flags, u32 *table, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) hw = clk_hw_register_mux_table(dev, name, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) num_parents, flags, reg, shift, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_mux_flags, table, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ERR_CAST(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) EXPORT_SYMBOL_GPL(clk_register_mux_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void clk_unregister_mux(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) EXPORT_SYMBOL_GPL(clk_unregister_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void clk_hw_unregister_mux(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) clk_hw_unregister(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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