^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2016 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define M10V_CLKSEL1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define M10V_PLL1 "pll1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define M10V_PLL1DIV2 "pll1-2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define M10V_PLL2 "pll2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define M10V_PLL2DIV2 "pll2-2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define M10V_PLL6 "pll6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define M10V_PLL6DIV2 "pll6-2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define M10V_PLL6DIV3 "pll6-3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define M10V_PLL7 "pll7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define M10V_PLL7DIV2 "pll7-2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define M10V_PLL7DIV5 "pll7-5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define M10V_PLL9 "pll9"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define M10V_PLL10 "pll10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define M10V_PLL10DIV2 "pll10-2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define M10V_PLL11 "pll11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define M10V_SPI_PARENT0 "spi-parent0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define M10V_SPI_PARENT1 "spi-parent1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define M10V_SPI_PARENT2 "spi-parent2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define M10V_UHS1CLK2_PARENT0 "uhs1clk2-parent0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define M10V_UHS1CLK2_PARENT2 "uhs1clk2-parent2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define M10V_UHS1CLK1_PARENT0 "uhs1clk1-parent0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define M10V_NFCLK_PARENT0 "nfclk-parent0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define M10V_NFCLK_PARENT1 "nfclk-parent1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define M10V_NFCLK_PARENT2 "nfclk-parent2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define M10V_NFCLK_PARENT3 "nfclk-parent3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define M10V_NFCLK_PARENT4 "nfclk-parent4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define M10V_NFCLK_PARENT5 "nfclk-parent5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define M10V_DCHREQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define M10V_UPOLL_RATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define M10V_UTIMEOUT 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define M10V_EMMCCLK_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define M10V_ACLK_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define M10V_HCLK_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define M10V_PCLK_ID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define M10V_RCLK_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define M10V_SPICLK_ID 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define M10V_NFCLK_ID 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define M10V_UHS1CLK2_ID 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define M10V_NUM_CLKS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define to_m10v_div(_hw) container_of(_hw, struct m10v_clk_divider, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct clk_hw_onecell_data *m10v_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static DEFINE_SPINLOCK(m10v_crglock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct m10v_clk_div_factors {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const struct clk_div_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int onecell_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct m10v_clk_div_fixed_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int onecell_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct m10v_clk_mux_factors {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int onecell_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct clk_div_table emmcclk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .val = 0, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .val = 1, .div = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .val = 2, .div = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .val = 3, .div = 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct clk_div_table mclk400_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct clk_div_table mclk200_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .val = 7, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct clk_div_table aclk400_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct clk_div_table aclk300_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .val = 1, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct clk_div_table aclk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .val = 7, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct clk_div_table aclkexs_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .val = 4, .div = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .val = 5, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .val = 7, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct clk_div_table hclk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .val = 7, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .val = 15, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct clk_div_table hclkbmh_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .val = 7, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct clk_div_table pclk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .val = 15, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .val = 31, .div = 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct clk_div_table rclk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { .val = 0, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .val = 1, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .val = 2, .div = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .val = 3, .div = 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct clk_div_table uhs1clk0_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .val = 1, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .val = 4, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct clk_div_table uhs2clk_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .val = 0, .div = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .val = 1, .div = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { .val = 2, .div = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .val = 3, .div = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .val = 4, .div = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .val = 5, .div = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { .val = 6, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .val = 7, .div = 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static u32 spi_mux_table[] = {0, 1, 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const char * const spi_mux_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) M10V_SPI_PARENT0, M10V_SPI_PARENT1, M10V_SPI_PARENT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static u32 uhs1clk2_mux_table[] = {2, 3, 4, 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const char * const uhs1clk2_mux_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) M10V_UHS1CLK2_PARENT0, M10V_UHS1CLK2_PARENT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) M10V_UHS1CLK2_PARENT2, M10V_PLL6DIV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static u32 uhs1clk1_mux_table[] = {3, 4, 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const char * const uhs1clk1_mux_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) M10V_UHS1CLK1_PARENT0, M10V_UHS1CLK1_PARENT1, M10V_PLL6DIV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static u32 nfclk_mux_table[] = {0, 1, 2, 3, 4, 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const char * const nfclk_mux_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) M10V_NFCLK_PARENT0, M10V_NFCLK_PARENT1, M10V_NFCLK_PARENT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) M10V_NFCLK_PARENT3, M10V_NFCLK_PARENT4, M10V_NFCLK_PARENT5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct m10v_clk_div_fixed_data m10v_pll_fixed_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {M10V_PLL1, NULL, 1, 40, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {M10V_PLL2, NULL, 1, 30, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {M10V_PLL6, NULL, 1, 35, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {M10V_PLL7, NULL, 1, 40, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {M10V_PLL9, NULL, 1, 33, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {M10V_PLL10, NULL, 5, 108, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {M10V_PLL10DIV2, M10V_PLL10, 2, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {M10V_PLL11, NULL, 2, 75, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct m10v_clk_div_fixed_data m10v_div_fixed_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {"usb2", NULL, 2, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {"pcisuppclk", NULL, 20, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {M10V_PLL1DIV2, M10V_PLL1, 2, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {M10V_PLL2DIV2, M10V_PLL2, 2, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {M10V_PLL6DIV2, M10V_PLL6, 2, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {M10V_PLL6DIV3, M10V_PLL6, 3, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {M10V_PLL7DIV2, M10V_PLL7, 2, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {M10V_PLL7DIV5, M10V_PLL7, 5, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {"ca7wd", M10V_PLL2DIV2, 12, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {"pclkca7wd", M10V_PLL1DIV2, 16, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {M10V_SPI_PARENT0, M10V_PLL10DIV2, 2, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {M10V_SPI_PARENT1, M10V_PLL10DIV2, 4, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {M10V_SPI_PARENT2, M10V_PLL7DIV2, 8, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {M10V_UHS1CLK2_PARENT0, M10V_PLL7, 4, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {M10V_UHS1CLK2_PARENT1, M10V_PLL7, 8, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {M10V_UHS1CLK2_PARENT2, M10V_PLL7, 16, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {M10V_UHS1CLK1_PARENT0, M10V_PLL7, 8, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {M10V_UHS1CLK1_PARENT1, M10V_PLL7, 16, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {M10V_NFCLK_PARENT0, M10V_PLL7DIV2, 8, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {M10V_NFCLK_PARENT1, M10V_PLL7DIV2, 10, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {M10V_NFCLK_PARENT2, M10V_PLL7DIV2, 13, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {M10V_NFCLK_PARENT3, M10V_PLL7DIV2, 16, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {M10V_NFCLK_PARENT4, M10V_PLL7DIV2, 40, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {M10V_NFCLK_PARENT5, M10V_PLL7DIV5, 10, 1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct m10v_clk_div_factors m10v_div_factor_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) M10V_EMMCCLK_ID},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {"pclk", M10V_PLL1DIV2, CLKSEL(9), 0, 7, pclk_table, 0, M10V_PCLK_ID},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {"uhs1clk0", M10V_PLL7, CLKSEL(1), 3, 5, uhs1clk0_table, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {"uhs2clk", M10V_PLL6DIV3, CLKSEL(1), 18, 4, uhs2clk_table, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct m10v_clk_mux_factors m10v_mux_factor_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {"spi", spi_mux_names, ARRAY_SIZE(spi_mux_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {"uhs1clk2", uhs1clk2_mux_names, ARRAY_SIZE(uhs1clk2_mux_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, M10V_UHS1CLK2_ID},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {"uhs1clk1", uhs1clk1_mux_names, ARRAY_SIZE(uhs1clk1_mux_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {"nfclk", nfclk_mux_names, ARRAY_SIZE(nfclk_mux_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static u8 m10v_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct clk_mux *mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val = readl(mux->reg) >> mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val &= mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int m10v_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct clk_mux *mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 write_en = BIT(fls(mux->mask) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spin_lock_irqsave(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __acquire(mux->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reg = readl(mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) reg &= ~(mux->mask << mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val = (val | write_en) << mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) writel(reg, mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spin_unlock_irqrestore(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __release(mux->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct clk_ops m10v_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .get_parent = m10v_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .set_parent = m10v_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct clk_hw *m10v_clk_hw_register_mux(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const char *name, const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 num_parents, unsigned long flags, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 shift, u32 mask, u8 clk_mux_flags, u32 *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) init.ops = &m10v_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mux->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mux->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mux->mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mux->flags = clk_mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mux->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mux->table = table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct m10v_clk_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const struct clk_div_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void __iomem *write_valid_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static unsigned long m10v_clk_divider_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct m10v_clk_divider *divider = to_m10v_div(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) val = readl(divider->reg) >> divider->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) val &= clk_div_mask(divider->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return divider_recalc_rate(hw, parent_rate, val, divider->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) divider->flags, divider->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static long m10v_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct m10v_clk_divider *divider = to_m10v_div(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* if read only, just return current value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (divider->flags & CLK_DIVIDER_READ_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) val = readl(divider->reg) >> divider->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val &= clk_div_mask(divider->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return divider_ro_round_rate(hw, rate, prate, divider->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) divider->width, divider->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return divider_round_rate(hw, rate, prate, divider->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) divider->width, divider->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct m10v_clk_divider *divider = to_m10v_div(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 write_en = BIT(divider->width - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) value = divider_get_val(rate, parent_rate, divider->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) divider->width, divider->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (divider->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) spin_lock_irqsave(divider->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) __acquire(divider->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) val = readl(divider->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) val &= ~(clk_div_mask(divider->width) << divider->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) val |= ((u32)value | write_en) << divider->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writel(val, divider->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (divider->write_valid_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writel(M10V_DCHREQ, divider->write_valid_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (readl_poll_timeout(divider->write_valid_reg, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) !val, M10V_UPOLL_RATE, M10V_UTIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pr_err("%s:%s couldn't stabilize\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __func__, clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (divider->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) spin_unlock_irqrestore(divider->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) __release(divider->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct clk_ops m10v_clk_divider_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .recalc_rate = m10v_clk_divider_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .round_rate = m10v_clk_divider_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .set_rate = m10v_clk_divider_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static struct clk_hw *m10v_clk_hw_register_divider(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) const char *name, const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 clk_divider_flags, const struct clk_div_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spinlock_t *lock, void __iomem *write_valid_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct m10v_clk_divider *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) div = kzalloc(sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) init.ops = &m10v_clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) div->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) div->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) div->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) div->flags = clk_divider_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) div->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) div->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) div->table = table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) div->write_valid_reg = write_valid_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* register the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hw = &div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) kfree(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void m10v_reg_div_pre(const struct m10v_clk_div_factors *factors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) void __iomem *write_valid_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * The registers on CLKSEL(9) or CLKSEL(10) need additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * writing to become valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if ((factors->offset == CLKSEL(9)) || (factors->offset == CLKSEL(10)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) write_valid_reg = base + CLKSEL(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) write_valid_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) hw = m10v_clk_hw_register_divider(NULL, factors->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) factors->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) base + factors->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) factors->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) factors->width, factors->div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) factors->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &m10v_crglock, write_valid_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (factors->onecell_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) clk_data->hws[factors->onecell_idx] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void m10v_reg_fixed_pre(const struct m10v_clk_div_fixed_data *factors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) const char *parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) const char *pn = factors->parent_name ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) factors->parent_name : parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) hw = clk_hw_register_fixed_factor(NULL, factors->name, pn, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) factors->mult, factors->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (factors->onecell_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) clk_data->hws[factors->onecell_idx] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static void m10v_reg_mux_pre(const struct m10v_clk_mux_factors *factors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct clk_hw_onecell_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hw = m10v_clk_hw_register_mux(NULL, factors->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) factors->parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) factors->num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) base + factors->offset, factors->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) factors->mask, factors->mux_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) factors->table, &m10v_crglock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (factors->onecell_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) clk_data->hws[factors->onecell_idx] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int m10v_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) for (id = 0; id < ARRAY_SIZE(m10v_div_factor_data); ++id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) m10v_reg_div_pre(&m10v_div_factor_data[id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) m10v_clk_data, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) for (id = 0; id < ARRAY_SIZE(m10v_div_fixed_data); ++id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) m10v_reg_fixed_pre(&m10v_div_fixed_data[id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) m10v_clk_data, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) for (id = 0; id < ARRAY_SIZE(m10v_mux_factor_data); ++id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) m10v_reg_mux_pre(&m10v_mux_factor_data[id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) m10v_clk_data, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) for (id = 0; id < M10V_NUM_CLKS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (IS_ERR(m10v_clk_data->hws[id]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return PTR_ERR(m10v_clk_data->hws[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const struct of_device_id m10v_clk_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { .compatible = "socionext,milbeaut-m10v-ccu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static struct platform_driver m10v_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .probe = m10v_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .name = "m10v-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .of_match_table = m10v_clk_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) builtin_platform_driver(m10v_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void __init m10v_cc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) m10v_clk_data = kzalloc(struct_size(m10v_clk_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) M10V_NUM_CLKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!m10v_clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) kfree(m10v_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!parent_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) kfree(m10v_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * This way all clocks fetched before the platform device probes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * except those we assign here for early use, will be deferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) for (id = 0; id < M10V_NUM_CLKS; id++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) m10v_clk_data->hws[id] = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * PLLs are set by bootloader so this driver registers them as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * fixed factor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) for (id = 0; id < ARRAY_SIZE(m10v_pll_fixed_data); ++id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) m10v_reg_fixed_pre(&m10v_pll_fixed_data[id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) m10v_clk_data, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * timer consumes "rclk" so it needs to register here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) hw = m10v_clk_hw_register_divider(NULL, "rclk", M10V_PLL10DIV2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) base + CLKSEL(1), 0, 3, 0, rclk_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) &m10v_crglock, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) m10v_clk_data->hws[M10V_RCLK_ID] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) m10v_clk_data->num = M10V_NUM_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, m10v_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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