Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <dt-bindings/clock/maxim,max9485.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MAX9485_NUM_CLKS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* This chip has only one register of 8 bit width. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MAX9485_FS_12KHZ	(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MAX9485_FS_32KHZ	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MAX9485_FS_44_1KHZ	(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MAX9485_FS_48KHZ	(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MAX9485_SCALE_256	(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MAX9485_SCALE_384	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MAX9485_SCALE_768	(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAX9485_DOUBLE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MAX9485_CLKOUT1_ENABLE	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MAX9485_CLKOUT2_ENABLE	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MAX9485_MCLK_ENABLE	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MAX9485_FREQ_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct max9485_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	unsigned long out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u8 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * Ordered by frequency. For frequency the hardware can generate with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * multiple settings, the one with lowest jitter is listed first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static const struct max9485_rate max9485_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{  3072000, MAX9485_FS_12KHZ   | MAX9485_SCALE_256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{  4608000, MAX9485_FS_12KHZ   | MAX9485_SCALE_384 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{  8192000, MAX9485_FS_32KHZ   | MAX9485_SCALE_256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{  9126000, MAX9485_FS_12KHZ   | MAX9485_SCALE_768 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ 11289600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ 12288000, MAX9485_FS_48KHZ   | MAX9485_SCALE_256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ 12288000, MAX9485_FS_32KHZ   | MAX9485_SCALE_384 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{ 16384000, MAX9485_FS_32KHZ   | MAX9485_SCALE_256 | MAX9485_DOUBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{ 16934400, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{ 18384000, MAX9485_FS_48KHZ   | MAX9485_SCALE_384 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ 22579200, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ 24576000, MAX9485_FS_48KHZ   | MAX9485_SCALE_256 | MAX9485_DOUBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ 24576000, MAX9485_FS_32KHZ   | MAX9485_SCALE_384 | MAX9485_DOUBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ 24576000, MAX9485_FS_32KHZ   | MAX9485_SCALE_768 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ 36864000, MAX9485_FS_48KHZ   | MAX9485_SCALE_384 | MAX9485_DOUBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ 36864000, MAX9485_FS_48KHZ   | MAX9485_SCALE_768 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ 49152000, MAX9485_FS_32KHZ   | MAX9485_SCALE_768 | MAX9485_DOUBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ 67737600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ 73728000, MAX9485_FS_48KHZ   | MAX9485_SCALE_768 | MAX9485_DOUBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{ } /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct max9485_driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct max9485_clk_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u8 enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct max9485_driver_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) struct max9485_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct clk *xclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u8 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct regulator *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct max9485_clk_hw hw[MAX9485_NUM_CLKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static inline struct max9485_clk_hw *to_max9485_clk(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return container_of(hw, struct max9485_clk_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int max9485_update_bits(struct max9485_driver_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			       u8 mask, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	drvdata->reg_value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	drvdata->reg_value |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	dev_dbg(&drvdata->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		"updating mask 0x%02x value 0x%02x -> 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		mask, value, drvdata->reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ret = i2c_master_send(drvdata->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			      &drvdata->reg_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			      sizeof(drvdata->reg_value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int max9485_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return max9485_update_bits(clk_hw->drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 				   clk_hw->enable_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				   clk_hw->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void max9485_clk_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * CLKOUT - configurable clock output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int max9485_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				   unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	const struct max9485_rate *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	for (entry = max9485_rates; entry->out != 0; entry++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		if (entry->out == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (entry->out == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return max9485_update_bits(clk_hw->drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				   MAX9485_FREQ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				   entry->reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static unsigned long max9485_clkout_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 						unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct max9485_driver_data *drvdata = clk_hw->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	const struct max9485_rate *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	for (entry = max9485_rates; entry->out != 0; entry++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (val == entry->reg_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			return entry->out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static long max9485_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				      unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	const struct max9485_rate *curr, *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	for (curr = max9485_rates; curr->out != 0; curr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		/* Exact matches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		if (curr->out == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		 * Find the first entry that has a frequency higher than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		 * requested one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (curr->out > rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			unsigned int mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			 * If this is the first entry, clamp the value to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			 * lowest possible frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			if (!prev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				return curr->out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			 * Otherwise, determine whether the previous entry or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			 * current one is closer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			mid = prev->out + ((curr->out - prev->out) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			return (mid > rate) ? prev->out : curr->out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		prev = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* If the last entry was still too high, clamp the value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return prev->out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct max9485_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	int parent_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	const struct clk_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u8 enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct max9485_clk max9485_clks[MAX9485_NUM_CLKS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	[MAX9485_MCLKOUT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.name = "mclkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.parent_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.enable_bit = MAX9485_MCLK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			.prepare	= max9485_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			.unprepare	= max9485_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	[MAX9485_CLKOUT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.name = "clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.parent_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			.set_rate	= max9485_clkout_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			.round_rate	= max9485_clkout_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			.recalc_rate	= max9485_clkout_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	[MAX9485_CLKOUT1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.name = "clkout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.parent_index = MAX9485_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.enable_bit = MAX9485_CLKOUT1_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			.prepare	= max9485_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			.unprepare	= max9485_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	[MAX9485_CLKOUT2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.name = "clkout2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.parent_index = MAX9485_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.enable_bit = MAX9485_CLKOUT2_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			.prepare	= max9485_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			.unprepare	= max9485_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) max9485_of_clk_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct max9485_driver_data *drvdata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return &drvdata->hw[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int max9485_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			     const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct max9485_driver_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	const char *xclk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	drvdata->xclk = devm_clk_get(dev, "xclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (IS_ERR(drvdata->xclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return PTR_ERR(drvdata->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	xclk_name = __clk_get_name(drvdata->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	drvdata->supply = devm_regulator_get(dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (IS_ERR(drvdata->supply))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return PTR_ERR(drvdata->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	ret = regulator_enable(drvdata->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	drvdata->reset_gpio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (IS_ERR(drvdata->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return PTR_ERR(drvdata->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	i2c_set_clientdata(client, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	drvdata->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ret = i2c_master_recv(drvdata->client, &drvdata->reg_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			      sizeof(drvdata->reg_value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		dev_warn(dev, "Unable to read device register: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	for (i = 0; i < MAX9485_NUM_CLKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		int parent_index = max9485_clks[i].parent_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		if (of_property_read_string_index(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 						  "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 						  i, &name) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			drvdata->hw[i].init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			drvdata->hw[i].init.name = max9485_clks[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		drvdata->hw[i].init.ops = &max9485_clks[i].ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		drvdata->hw[i].init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		drvdata->hw[i].init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		if (parent_index > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			drvdata->hw[i].init.parent_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				&drvdata->hw[parent_index].init.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			drvdata->hw[i].init.flags |= CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			drvdata->hw[i].init.parent_names = &xclk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		drvdata->hw[i].hw.init = &drvdata->hw[i].init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		drvdata->hw[i].drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		ret = devm_clk_hw_register(dev, &drvdata->hw[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return devm_of_clk_add_hw_provider(dev, max9485_of_clk_get, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int __maybe_unused max9485_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	gpiod_set_value_cansleep(drvdata->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int __maybe_unused max9485_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	gpiod_set_value_cansleep(drvdata->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ret = i2c_master_send(client, &drvdata->reg_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			      sizeof(drvdata->reg_value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct dev_pm_ops max9485_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	SET_SYSTEM_SLEEP_PM_OPS(max9485_suspend, max9485_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct of_device_id max9485_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	{ .compatible = "maxim,max9485", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_DEVICE_TABLE(of, max9485_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct i2c_device_id max9485_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	{ .name = "max9485", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_DEVICE_TABLE(i2c, max9485_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct i2c_driver max9485_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		.name		= "max9485",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		.pm		= &max9485_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.of_match_table	= max9485_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.probe = max9485_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	.id_table = max9485_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) module_i2c_driver(max9485_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_AUTHOR("Daniel Mack <daniel@zonque.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_DESCRIPTION("MAX9485 Programmable Audio Clock Generator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MODULE_LICENSE("GPL v2");