Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // clk-max77686.c - Clock driver for Maxim 77686/MAX77802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2012 Samsung Electornics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Jonghwa Lee <jonghwa3.lee@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/max77620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/max77686.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/max77686-private.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <dt-bindings/clock/maxim,max77686.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <dt-bindings/clock/maxim,max77802.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <dt-bindings/clock/maxim,max77620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) enum max77686_chip_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	CHIP_MAX77686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	CHIP_MAX77802,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	CHIP_MAX77620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct max77686_hw_clk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32 clk_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct max77686_clk_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct clk_init_data clk_idata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	const struct max77686_hw_clk_info *clk_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct max77686_clk_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	enum max77686_chip_name chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct max77686_clk_init_data *max_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	size_t num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static const struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) max77686_hw_clk_info max77686_hw_clks_info[MAX77686_CLKS_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	[MAX77686_CLK_AP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.name = "32khz_ap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.clk_reg = MAX77686_REG_32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.clk_enable_mask = BIT(MAX77686_CLK_AP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	[MAX77686_CLK_CP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.name = "32khz_cp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.clk_reg = MAX77686_REG_32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.clk_enable_mask = BIT(MAX77686_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	[MAX77686_CLK_PMIC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.name = "32khz_pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.clk_reg = MAX77686_REG_32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.clk_enable_mask = BIT(MAX77686_CLK_PMIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static const struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) max77686_hw_clk_info max77802_hw_clks_info[MAX77802_CLKS_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	[MAX77802_CLK_32K_AP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.name = "32khz_ap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.clk_reg = MAX77802_REG_32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.clk_enable_mask = BIT(MAX77802_CLK_32K_AP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	[MAX77802_CLK_32K_CP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.name = "32khz_cp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.clk_reg = MAX77802_REG_32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.clk_enable_mask = BIT(MAX77802_CLK_32K_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static const struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) max77686_hw_clk_info max77620_hw_clks_info[MAX77620_CLKS_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	[MAX77620_CLK_32K_OUT0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.name = "32khz_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.clk_reg = MAX77620_REG_CNFG1_32K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.clk_enable_mask = MAX77620_CNFG1_32K_OUT0_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static struct max77686_clk_init_data *to_max77686_clk_init_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	return container_of(hw, struct max77686_clk_init_data, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int max77686_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				  max77686->clk_info->clk_enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				  max77686->clk_info->clk_enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void max77686_clk_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			   max77686->clk_info->clk_enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			   ~max77686->clk_info->clk_enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int max77686_clk_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ret = regmap_read(max77686->regmap, max77686->clk_info->clk_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return val & max77686->clk_info->clk_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static unsigned long max77686_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 					  unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct clk_ops max77686_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.prepare	= max77686_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.unprepare	= max77686_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.is_prepared	= max77686_clk_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.recalc_rate	= max77686_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) of_clk_max77686_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct max77686_clk_driver_data *drv_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (idx >= drv_data->num_clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return &drv_data->max_clk_data[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int max77686_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct device *parent = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	const struct platform_device_id *id = platform_get_device_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct max77686_clk_driver_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	const struct max77686_hw_clk_info *hw_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int i, ret, num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (!drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	regmap = dev_get_regmap(parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		dev_err(dev, "Failed to get rtc regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	drv_data->chip = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	switch (drv_data->chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case CHIP_MAX77686:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		num_clks = MAX77686_CLKS_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		hw_clks = max77686_hw_clks_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	case CHIP_MAX77802:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		num_clks = MAX77802_CLKS_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		hw_clks = max77802_hw_clks_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	case CHIP_MAX77620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		num_clks = MAX77620_CLKS_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		hw_clks = max77620_hw_clks_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		dev_err(dev, "Unknown Chip ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	drv_data->num_clks = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	drv_data->max_clk_data = devm_kcalloc(dev, num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 					      sizeof(*drv_data->max_clk_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					      GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (!drv_data->max_clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		struct max77686_clk_init_data *max_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		max_clk_data = &drv_data->max_clk_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		max_clk_data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		max_clk_data->clk_info = &hw_clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		max_clk_data->clk_idata.flags = hw_clks[i].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		max_clk_data->clk_idata.ops = &max77686_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		if (parent->of_node &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		    !of_property_read_string_index(parent->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 						   "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 						   i, &clk_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			max_clk_data->clk_idata.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			max_clk_data->clk_idata.name = hw_clks[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		max_clk_data->hw.init = &max_clk_data->clk_idata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		ret = devm_clk_hw_register(dev, &max_clk_data->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			dev_err(dev, "Failed to clock register: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		ret = devm_clk_hw_register_clkdev(dev, &max_clk_data->hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 						  max_clk_data->clk_idata.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 						  NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			dev_err(dev, "Failed to clkdev register: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (parent->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		ret = devm_of_clk_add_hw_provider(dev, of_clk_max77686_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 						  drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			dev_err(dev, "Failed to register OF clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* MAX77802: Enable low-jitter mode on the 32khz clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (drv_data->chip == CHIP_MAX77802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		ret = regmap_update_bits(regmap, MAX77802_REG_32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 					 1 << MAX77802_CLOCK_LOW_JITTER_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 					 1 << MAX77802_CLOCK_LOW_JITTER_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			dev_err(dev, "Failed to config low-jitter: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct platform_device_id max77686_clk_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	{ "max77686-clk", .driver_data = CHIP_MAX77686, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	{ "max77802-clk", .driver_data = CHIP_MAX77802, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	{ "max77620-clock", .driver_data = CHIP_MAX77620, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_DEVICE_TABLE(platform, max77686_clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct platform_driver max77686_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.name  = "max77686-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.probe = max77686_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.id_table = max77686_clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) module_platform_driver(max77686_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_DESCRIPTION("MAXIM 77686 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_AUTHOR("Jonghwa Lee <jonghwa3.lee@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_LICENSE("GPL");